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Commit b33c4b4b authored by Cong Dang's avatar Cong Dang Committed by Geert Uytterhoeven
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pinctrl: renesas: r8a779h0: Add MSIOF pins, groups, functions 

Add pins, groups and functions for the Clock-Synchronized Serial
Interfaces with FIFO (MSIOF) on the Renesas R-Car V4M (R8A779H0) SoC.
Signed-off-by: default avatarCong Dang <cong.dang.xn@renesas.com>
Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/cbfc61f0c02e9dbeec0ea689e10bdd5ebf5bf1e3.1706264667.git.geert+renesas@glider.be
parent 2a9d0273
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drivers/pinctrl/renesas/pfc-r8a779h0.c
View file @ b33c4b4b
......@@ -1642,6 +1642,270 @@ static const unsigned int mmc_ds_mux[] = {
MMC_DS_MARK,
};
/* - MSIOF0 ----------------------------------------------------------------- */
static const unsigned int msiof0_clk_pins[] = {
/* MSIOF0_SCK */
RCAR_GP_PIN(1, 10),
};
static const unsigned int msiof0_clk_mux[] = {
MSIOF0_SCK_MARK,
};
static const unsigned int msiof0_sync_pins[] = {
/* MSIOF0_SYNC */
RCAR_GP_PIN(1, 8),
};
static const unsigned int msiof0_sync_mux[] = {
MSIOF0_SYNC_MARK,
};
static const unsigned int msiof0_ss1_pins[] = {
/* MSIOF0_SS1 */
RCAR_GP_PIN(1, 7),
};
static const unsigned int msiof0_ss1_mux[] = {
MSIOF0_SS1_MARK,
};
static const unsigned int msiof0_ss2_pins[] = {
/* MSIOF0_SS2 */
RCAR_GP_PIN(1, 6),
};
static const unsigned int msiof0_ss2_mux[] = {
MSIOF0_SS2_MARK,
};
static const unsigned int msiof0_txd_pins[] = {
/* MSIOF0_TXD */
RCAR_GP_PIN(1, 9),
};
static const unsigned int msiof0_txd_mux[] = {
MSIOF0_TXD_MARK,
};
static const unsigned int msiof0_rxd_pins[] = {
/* MSIOF0_RXD */
RCAR_GP_PIN(1, 11),
};
static const unsigned int msiof0_rxd_mux[] = {
MSIOF0_RXD_MARK,
};
/* - MSIOF1 ----------------------------------------------------------------- */
static const unsigned int msiof1_clk_pins[] = {
/* MSIOF1_SCK */
RCAR_GP_PIN(1, 3),
};
static const unsigned int msiof1_clk_mux[] = {
MSIOF1_SCK_MARK,
};
static const unsigned int msiof1_sync_pins[] = {
/* MSIOF1_SYNC */
RCAR_GP_PIN(1, 2),
};
static const unsigned int msiof1_sync_mux[] = {
MSIOF1_SYNC_MARK,
};
static const unsigned int msiof1_ss1_pins[] = {
/* MSIOF1_SS1 */
RCAR_GP_PIN(1, 1),
};
static const unsigned int msiof1_ss1_mux[] = {
MSIOF1_SS1_MARK,
};
static const unsigned int msiof1_ss2_pins[] = {
/* MSIOF1_SS2 */
RCAR_GP_PIN(1, 0),
};
static const unsigned int msiof1_ss2_mux[] = {
MSIOF1_SS2_MARK,
};
static const unsigned int msiof1_txd_pins[] = {
/* MSIOF1_TXD */
RCAR_GP_PIN(1, 4),
};
static const unsigned int msiof1_txd_mux[] = {
MSIOF1_TXD_MARK,
};
static const unsigned int msiof1_rxd_pins[] = {
/* MSIOF1_RXD */
RCAR_GP_PIN(1, 5),
};
static const unsigned int msiof1_rxd_mux[] = {
MSIOF1_RXD_MARK,
};
/* - MSIOF2 ----------------------------------------------------------------- */
static const unsigned int msiof2_clk_pins[] = {
/* MSIOF2_SCK */
RCAR_GP_PIN(0, 17),
};
static const unsigned int msiof2_clk_mux[] = {
MSIOF2_SCK_MARK,
};
static const unsigned int msiof2_sync_pins[] = {
/* MSIOF2_SYNC */
RCAR_GP_PIN(0, 15),
};
static const unsigned int msiof2_sync_mux[] = {
MSIOF2_SYNC_MARK,
};
static const unsigned int msiof2_ss1_pins[] = {
/* MSIOF2_SS1 */
RCAR_GP_PIN(0, 14),
};
static const unsigned int msiof2_ss1_mux[] = {
MSIOF2_SS1_MARK,
};
static const unsigned int msiof2_ss2_pins[] = {
/* MSIOF2_SS2 */
RCAR_GP_PIN(0, 13),
};
static const unsigned int msiof2_ss2_mux[] = {
MSIOF2_SS2_MARK,
};
static const unsigned int msiof2_txd_pins[] = {
/* MSIOF2_TXD */
RCAR_GP_PIN(0, 16),
};
static const unsigned int msiof2_txd_mux[] = {
MSIOF2_TXD_MARK,
};
static const unsigned int msiof2_rxd_pins[] = {
/* MSIOF2_RXD */
RCAR_GP_PIN(0, 18),
};
static const unsigned int msiof2_rxd_mux[] = {
MSIOF2_RXD_MARK,
};
/* - MSIOF3 ----------------------------------------------------------------- */
static const unsigned int msiof3_clk_pins[] = {
/* MSIOF3_SCK */
RCAR_GP_PIN(0, 3),
};
static const unsigned int msiof3_clk_mux[] = {
MSIOF3_SCK_MARK,
};
static const unsigned int msiof3_sync_pins[] = {
/* MSIOF3_SYNC */
RCAR_GP_PIN(0, 6),
};
static const unsigned int msiof3_sync_mux[] = {
MSIOF3_SYNC_MARK,
};
static const unsigned int msiof3_ss1_pins[] = {
/* MSIOF3_SS1 */
RCAR_GP_PIN(0, 1),
};
static const unsigned int msiof3_ss1_mux[] = {
MSIOF3_SS1_MARK,
};
static const unsigned int msiof3_ss2_pins[] = {
/* MSIOF3_SS2 */
RCAR_GP_PIN(0, 2),
};
static const unsigned int msiof3_ss2_mux[] = {
MSIOF3_SS2_MARK,
};
static const unsigned int msiof3_txd_pins[] = {
/* MSIOF3_TXD */
RCAR_GP_PIN(0, 4),
};
static const unsigned int msiof3_txd_mux[] = {
MSIOF3_TXD_MARK,
};
static const unsigned int msiof3_rxd_pins[] = {
/* MSIOF3_RXD */
RCAR_GP_PIN(0, 5),
};
static const unsigned int msiof3_rxd_mux[] = {
MSIOF3_RXD_MARK,
};
/* - MSIOF4 ----------------------------------------------------------------- */
static const unsigned int msiof4_clk_pins[] = {
/* MSIOF4_SCK */
RCAR_GP_PIN(1, 25),
};
static const unsigned int msiof4_clk_mux[] = {
MSIOF4_SCK_MARK,
};
static const unsigned int msiof4_sync_pins[] = {
/* MSIOF4_SYNC */
RCAR_GP_PIN(1, 28),
};
static const unsigned int msiof4_sync_mux[] = {
MSIOF4_SYNC_MARK,
};
static const unsigned int msiof4_ss1_pins[] = {
/* MSIOF4_SS1 */
RCAR_GP_PIN(1, 23),
};
static const unsigned int msiof4_ss1_mux[] = {
MSIOF4_SS1_MARK,
};
static const unsigned int msiof4_ss2_pins[] = {
/* MSIOF4_SS2 */
RCAR_GP_PIN(1, 24),
};
static const unsigned int msiof4_ss2_mux[] = {
MSIOF4_SS2_MARK,
};
static const unsigned int msiof4_txd_pins[] = {
/* MSIOF4_TXD */
RCAR_GP_PIN(1, 26),
};
static const unsigned int msiof4_txd_mux[] = {
MSIOF4_TXD_MARK,
};
static const unsigned int msiof4_rxd_pins[] = {
/* MSIOF4_RXD */
RCAR_GP_PIN(1, 27),
};
static const unsigned int msiof4_rxd_mux[] = {
MSIOF4_RXD_MARK,
};
/* - MSIOF5 ----------------------------------------------------------------- */
static const unsigned int msiof5_clk_pins[] = {
/* MSIOF5_SCK */
RCAR_GP_PIN(0, 11),
};
static const unsigned int msiof5_clk_mux[] = {
MSIOF5_SCK_MARK,
};
static const unsigned int msiof5_sync_pins[] = {
/* MSIOF5_SYNC */
RCAR_GP_PIN(0, 9),
};
static const unsigned int msiof5_sync_mux[] = {
MSIOF5_SYNC_MARK,
};
static const unsigned int msiof5_ss1_pins[] = {
/* MSIOF5_SS1 */
RCAR_GP_PIN(0, 8),
};
static const unsigned int msiof5_ss1_mux[] = {
MSIOF5_SS1_MARK,
};
static const unsigned int msiof5_ss2_pins[] = {
/* MSIOF5_SS2 */
RCAR_GP_PIN(0, 7),
};
static const unsigned int msiof5_ss2_mux[] = {
MSIOF5_SS2_MARK,
};
static const unsigned int msiof5_txd_pins[] = {
/* MSIOF5_TXD */
RCAR_GP_PIN(0, 10),
};
static const unsigned int msiof5_txd_mux[] = {
MSIOF5_TXD_MARK,
};
static const unsigned int msiof5_rxd_pins[] = {
/* MSIOF5_RXD */
RCAR_GP_PIN(0, 12),
};
static const unsigned int msiof5_rxd_mux[] = {
MSIOF5_RXD_MARK,
};
/* - QSPI0 ------------------------------------------------------------------ */
static const unsigned int qspi0_ctrl_pins[] = {
/* SPCLK, SSL */
......@@ -1896,6 +2160,48 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(mmc_wp),
SH_PFC_PIN_GROUP(mmc_ds),
SH_PFC_PIN_GROUP(msiof0_clk),
SH_PFC_PIN_GROUP(msiof0_sync),
SH_PFC_PIN_GROUP(msiof0_ss1),
SH_PFC_PIN_GROUP(msiof0_ss2),
SH_PFC_PIN_GROUP(msiof0_txd),
SH_PFC_PIN_GROUP(msiof0_rxd),
SH_PFC_PIN_GROUP(msiof1_clk),
SH_PFC_PIN_GROUP(msiof1_sync),
SH_PFC_PIN_GROUP(msiof1_ss1),
SH_PFC_PIN_GROUP(msiof1_ss2),
SH_PFC_PIN_GROUP(msiof1_txd),
SH_PFC_PIN_GROUP(msiof1_rxd),
SH_PFC_PIN_GROUP(msiof2_clk),
SH_PFC_PIN_GROUP(msiof2_sync),
SH_PFC_PIN_GROUP(msiof2_ss1),
SH_PFC_PIN_GROUP(msiof2_ss2),
SH_PFC_PIN_GROUP(msiof2_txd),
SH_PFC_PIN_GROUP(msiof2_rxd),
SH_PFC_PIN_GROUP(msiof3_clk),
SH_PFC_PIN_GROUP(msiof3_sync),
SH_PFC_PIN_GROUP(msiof3_ss1),
SH_PFC_PIN_GROUP(msiof3_ss2),
SH_PFC_PIN_GROUP(msiof3_txd),
SH_PFC_PIN_GROUP(msiof3_rxd),
SH_PFC_PIN_GROUP(msiof4_clk),
SH_PFC_PIN_GROUP(msiof4_sync),
SH_PFC_PIN_GROUP(msiof4_ss1),
SH_PFC_PIN_GROUP(msiof4_ss2),
SH_PFC_PIN_GROUP(msiof4_txd),
SH_PFC_PIN_GROUP(msiof4_rxd),
SH_PFC_PIN_GROUP(msiof5_clk),
SH_PFC_PIN_GROUP(msiof5_sync),
SH_PFC_PIN_GROUP(msiof5_ss1),
SH_PFC_PIN_GROUP(msiof5_ss2),
SH_PFC_PIN_GROUP(msiof5_txd),
SH_PFC_PIN_GROUP(msiof5_rxd),
SH_PFC_PIN_GROUP(qspi0_ctrl),
BUS_DATA_PIN_GROUP(qspi0_data, 2),
BUS_DATA_PIN_GROUP(qspi0_data, 4),
......@@ -2017,6 +2323,60 @@ static const char * const mmc_groups[] = {
"mmc_ds",
};
static const char * const msiof0_groups[] = {
"msiof0_clk",
"msiof0_sync",
"msiof0_ss1",
"msiof0_ss2",
"msiof0_txd",
"msiof0_rxd",
};
static const char * const msiof1_groups[] = {
"msiof1_clk",
"msiof1_sync",
"msiof1_ss1",
"msiof1_ss2",
"msiof1_txd",
"msiof1_rxd",
};
static const char * const msiof2_groups[] = {
"msiof2_clk",
"msiof2_sync",
"msiof2_ss1",
"msiof2_ss2",
"msiof2_txd",
"msiof2_rxd",
};
static const char * const msiof3_groups[] = {
"msiof3_clk",
"msiof3_sync",
"msiof3_ss1",
"msiof3_ss2",
"msiof3_txd",
"msiof3_rxd",
};
static const char * const msiof4_groups[] = {
"msiof4_clk",
"msiof4_sync",
"msiof4_ss1",
"msiof4_ss2",
"msiof4_txd",
"msiof4_rxd",
};
static const char * const msiof5_groups[] = {
"msiof5_clk",
"msiof5_sync",
"msiof5_ss1",
"msiof5_ss2",
"msiof5_txd",
"msiof5_rxd",
};
static const char * const qspi0_groups[] = {
"qspi0_ctrl",
"qspi0_data2",
......@@ -2084,6 +2444,13 @@ static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(mmc),
SH_PFC_FUNCTION(msiof0),
SH_PFC_FUNCTION(msiof1),
SH_PFC_FUNCTION(msiof2),
SH_PFC_FUNCTION(msiof3),
SH_PFC_FUNCTION(msiof4),
SH_PFC_FUNCTION(msiof5),
SH_PFC_FUNCTION(qspi0),
SH_PFC_FUNCTION(qspi1),
......
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