[patch] Intel ICH7 DID's, PIRQ and PATA support

From: Jason Gaston <jason.d.gaston@intel.com>

This patch adds the Intel ICH7 DID's to the pci_ids.h file
and updates the piix driver and related files for PATA support.

bart: this patch also adds PIRQ support
Signed-off-by: default avatarBartlomiej Zolnierkiewicz <bzolnier@gmail.com>
parent 5b9470db
...@@ -491,6 +491,8 @@ static __init int intel_router_probe(struct irq_router *r, struct pci_dev *route ...@@ -491,6 +491,8 @@ static __init int intel_router_probe(struct irq_router *r, struct pci_dev *route
case PCI_DEVICE_ID_INTEL_ESB_1: case PCI_DEVICE_ID_INTEL_ESB_1:
case PCI_DEVICE_ID_INTEL_ICH6_0: case PCI_DEVICE_ID_INTEL_ICH6_0:
case PCI_DEVICE_ID_INTEL_ICH6_1: case PCI_DEVICE_ID_INTEL_ICH6_1:
case PCI_DEVICE_ID_INTEL_ICH7_0:
case PCI_DEVICE_ID_INTEL_ICH7_1:
r->name = "PIIX/ICH"; r->name = "PIIX/ICH";
r->get = pirq_piix_get; r->get = pirq_piix_get;
r->set = pirq_piix_set; r->set = pirq_piix_set;
......
...@@ -134,6 +134,7 @@ static u8 piix_ratemask (ide_drive_t *drive) ...@@ -134,6 +134,7 @@ static u8 piix_ratemask (ide_drive_t *drive)
case PCI_DEVICE_ID_INTEL_82801EB_11: case PCI_DEVICE_ID_INTEL_82801EB_11:
case PCI_DEVICE_ID_INTEL_ESB_2: case PCI_DEVICE_ID_INTEL_ESB_2:
case PCI_DEVICE_ID_INTEL_ICH6_19: case PCI_DEVICE_ID_INTEL_ICH6_19:
case PCI_DEVICE_ID_INTEL_ICH7_21:
mode = 3; mode = 3;
break; break;
/* UDMA 66 capable */ /* UDMA 66 capable */
...@@ -445,6 +446,7 @@ static unsigned int __devinit init_chipset_piix (struct pci_dev *dev, const char ...@@ -445,6 +446,7 @@ static unsigned int __devinit init_chipset_piix (struct pci_dev *dev, const char
case PCI_DEVICE_ID_INTEL_82801E_11: case PCI_DEVICE_ID_INTEL_82801E_11:
case PCI_DEVICE_ID_INTEL_ESB_2: case PCI_DEVICE_ID_INTEL_ESB_2:
case PCI_DEVICE_ID_INTEL_ICH6_19: case PCI_DEVICE_ID_INTEL_ICH6_19:
case PCI_DEVICE_ID_INTEL_ICH7_21:
{ {
unsigned int extra = 0; unsigned int extra = 0;
pci_read_config_dword(dev, 0x54, &extra); pci_read_config_dword(dev, 0x54, &extra);
...@@ -611,6 +613,7 @@ static struct pci_device_id piix_pci_tbl[] = { ...@@ -611,6 +613,7 @@ static struct pci_device_id piix_pci_tbl[] = {
#endif #endif
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 19}, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 19},
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_19, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 20}, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_19, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 20},
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_21, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 21},
{ 0, }, { 0, },
}; };
MODULE_DEVICE_TABLE(pci, piix_pci_tbl); MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
......
...@@ -57,7 +57,8 @@ static ide_pci_device_t piix_pci_info[] __devinitdata = { ...@@ -57,7 +57,8 @@ static ide_pci_device_t piix_pci_info[] __devinitdata = {
/* 17 */ DECLARE_PIIX_DEV("ICH4"), /* 17 */ DECLARE_PIIX_DEV("ICH4"),
/* 18 */ DECLARE_PIIX_DEV("ICH5-SATA"), /* 18 */ DECLARE_PIIX_DEV("ICH5-SATA"),
/* 19 */ DECLARE_PIIX_DEV("ICH5"), /* 19 */ DECLARE_PIIX_DEV("ICH5"),
/* 20 */ DECLARE_PIIX_DEV("ICH6") /* 20 */ DECLARE_PIIX_DEV("ICH6"),
/* 21 */ DECLARE_PIIX_DEV("ICH7"),
}; };
#endif /* PIIX_H */ #endif /* PIIX_H */
...@@ -2228,6 +2228,30 @@ ...@@ -2228,6 +2228,30 @@
#define PCI_DEVICE_ID_INTEL_ICH6_17 0x266d #define PCI_DEVICE_ID_INTEL_ICH6_17 0x266d
#define PCI_DEVICE_ID_INTEL_ICH6_18 0x266e #define PCI_DEVICE_ID_INTEL_ICH6_18 0x266e
#define PCI_DEVICE_ID_INTEL_ICH6_19 0x266f #define PCI_DEVICE_ID_INTEL_ICH6_19 0x266f
#define PCI_DEVICE_ID_INTEL_ICH7_0 0x27b0
#define PCI_DEVICE_ID_INTEL_ICH7_1 0x27b1
#define PCI_DEVICE_ID_INTEL_ICH7_2 0x27c0
#define PCI_DEVICE_ID_INTEL_ICH7_3 0x27c1
#define PCI_DEVICE_ID_INTEL_ICH7_4 0x27c2
#define PCI_DEVICE_ID_INTEL_ICH7_5 0x27c4
#define PCI_DEVICE_ID_INTEL_ICH7_6 0x27c5
#define PCI_DEVICE_ID_INTEL_ICH7_7 0x27c8
#define PCI_DEVICE_ID_INTEL_ICH7_8 0x27c9
#define PCI_DEVICE_ID_INTEL_ICH7_9 0x27ca
#define PCI_DEVICE_ID_INTEL_ICH7_10 0x27cb
#define PCI_DEVICE_ID_INTEL_ICH7_11 0x27cc
#define PCI_DEVICE_ID_INTEL_ICH7_12 0x27d0
#define PCI_DEVICE_ID_INTEL_ICH7_13 0x27d2
#define PCI_DEVICE_ID_INTEL_ICH7_14 0x27d4
#define PCI_DEVICE_ID_INTEL_ICH7_15 0x27d6
#define PCI_DEVICE_ID_INTEL_ICH7_16 0x27d8
#define PCI_DEVICE_ID_INTEL_ICH7_17 0x27da
#define PCI_DEVICE_ID_INTEL_ICH7_18 0x27dc
#define PCI_DEVICE_ID_INTEL_ICH7_19 0x27dd
#define PCI_DEVICE_ID_INTEL_ICH7_20 0x27de
#define PCI_DEVICE_ID_INTEL_ICH7_21 0x27df
#define PCI_DEVICE_ID_INTEL_ICH7_22 0x27e0
#define PCI_DEVICE_ID_INTEL_ICH7_23 0x27e2
#define PCI_DEVICE_ID_INTEL_82855PM_HB 0x3340 #define PCI_DEVICE_ID_INTEL_82855PM_HB 0x3340
#define PCI_DEVICE_ID_INTEL_82830_HB 0x3575 #define PCI_DEVICE_ID_INTEL_82830_HB 0x3575
#define PCI_DEVICE_ID_INTEL_82830_CGC 0x3577 #define PCI_DEVICE_ID_INTEL_82830_CGC 0x3577
......
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