Commit b4791e69 authored by Danny Lin's avatar Danny Lin Committed by Bjorn Andersson

arm64: dts: qcom: sm8250: Define CPU topology

sm8250 has a big.LITTLE CPU setup with DynamIQ, so all cores are within
the same CPU cluster and LLC (Last-Level Cache) domain. Define this
topology to help the scheduler make decisions.
Signed-off-by: default avatarDanny Lin <danny@kdrag0n.dev>
Link: https://lore.kernel.org/r/20210112013255.415253-1-danny@kdrag0n.devSigned-off-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
parent 3716a583
......@@ -203,6 +203,42 @@ L2_700: l2-cache {
next-level-cache = <&L3_0>;
};
};
cpu-map {
cluster0 {
core0 {
cpu = <&CPU0>;
};
core1 {
cpu = <&CPU1>;
};
core2 {
cpu = <&CPU2>;
};
core3 {
cpu = <&CPU3>;
};
core4 {
cpu = <&CPU4>;
};
core5 {
cpu = <&CPU5>;
};
core6 {
cpu = <&CPU6>;
};
core7 {
cpu = <&CPU7>;
};
};
};
};
firmware {
......
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