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Commit b4b50fd7 authored by Linus Torvalds's avatar Linus Torvalds
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Merge tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc 

Pull ARM SoC platform changes from Olof Johansson:
 "This branch contains mostly additions and changes to platform
  enablement and SoC-level drivers.  Since there's sometimes a
  dependency on device-tree changes, there's also a fair amount of
  those in this branch.

  Pieces worth mentioning are:

   - Mbus driver for Marvell platforms, allowing kernel configuration
     and resource allocation of on-chip peripherals.
   - Enablement of the mbus infrastructure from Marvell PCI-e drivers.
   - Preparation of MSI support for Marvell platforms.
   - Addition of new PCI-e host controller driver for Tegra platforms
   - Some churn caused by sharing of macro names between i.MX 6Q and 6DL
     platforms in the device tree sources and header files.
   - Various suspend/PM updates for Tegra, including LP1 support.
   - Versatile Express support for MCPM, part of big little support.
   - Allwinner platform support for A20 and A31 SoCs (dual and quad
     Cortex-A7)
   - OMAP2+ support for DRA7, a new Cortex-A15-based SoC.

  The code that touches other architectures are patches moving MSI
  arch-specific functions over to weak symbols and removal of
  ARCH_SUPPORTS_MSI, acked by PCI maintainers"

* tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (266 commits)
  tegra-cpuidle: provide stub when !CONFIG_CPU_IDLE
  PCI: tegra: replace devm_request_and_ioremap by devm_ioremap_resource
  ARM: tegra: Drop ARCH_SUPPORTS_MSI and sort list
  ARM: dts: vf610-twr: enable i2c0 device
  ARM: dts: i.MX51: Add one more I2C2 pinmux entry
  ARM: dts: i.MX51: Move pins configuration under "iomuxc" label
  ARM: dtsi: imx6qdl-sabresd: Add USB OTG vbus pin to pinctrl_hog
  ARM: dtsi: imx6qdl-sabresd: Add USB host 1 VBUS regulator
  ARM: dts: imx27-phytec-phycore-som: Enable AUDMUX
  ARM: dts: i.MX27: Disable AUDMUX in the template
  ARM: dts: wandboard: Add support for SDIO bcm4329
  ARM: i.MX5 clocks: Remove optional clock setup (CKIH1) from i.MX51 template
  ARM: dts: imx53-qsb: Make USBH1 functional
  ARM i.MX6Q: dts: Enable I2C1 with EEPROM and PMIC on Phytec phyFLEX-i.MX6 Ouad module
  ARM i.MX6Q: dts: Enable SPI NOR flash on Phytec phyFLEX-i.MX6 Ouad module
  ARM: dts: imx6qdl-sabresd: Add touchscreen support
  ARM: imx: add ocram clock for imx53
  ARM: dts: imx: ocram size is different between imx6q and imx6dl
  ARM: dts: imx27-phytec-phycore-som: Fix regulator settings
  ARM: dts: i.MX27: Remove clock name from CPU node
  ...
parents dccfd1e4 f97c43bb
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Showing with 12546 additions and 6424 deletions
Documentation/devicetree/bindings/arm/omap/omap.txt
View file @ b4b50fd7
......@@ -59,3 +59,6 @@ Boards:
- AM43x EPOS EVM
compatible = "ti,am43x-epos-evm", "ti,am4372", "ti,am43"
- DRA7 EVM: Software Developement Board for DRA7XX
compatible = "ti,dra7-evm", "ti,dra7"
Documentation/devicetree/bindings/arm/vexpress-scc.txt 0 → 100644
View file @ b4b50fd7
ARM Versatile Express Serial Configuration Controller
-----------------------------------------------------
Test chips for ARM Versatile Express platform implement SCC (Serial
Configuration Controller) interface, used to set initial conditions
for the test chip.
In some cases its registers are also mapped in normal address space
and can be used to obtain runtime information about the chip internals
(like silicon temperature sensors) and as interface to other subsystems
like platform configuration control and power management.
Required properties:
- compatible value: "arm,vexpress-scc,<model>", "arm,vexpress-scc";
where <model> is the full tile model name (as used
in the tile's Technical Reference Manual),
eg. for Coretile Express A15x2 A7x3 (V2P-CA15_A7):
compatible = "arm,vexpress-scc,v2p-ca15_a7", "arm,vexpress-scc";
Optional properties:
- reg: when the SCC is memory mapped, physical address and size of the
registers window
- interrupts: when the SCC can generate a system-level interrupt
Example:
scc@7fff0000 {
compatible = "arm,vexpress-scc,v2p-ca15_a7", "arm,vexpress-scc";
reg = <0 0x7fff0000 0 0x1000>;
interrupts = <0 95 4>;
};
Documentation/devicetree/bindings/bus/imx-weim.txt
View file @ b4b50fd7
......@@ -8,7 +8,7 @@ The actual devices are instantiated from the child nodes of a WEIM node.
Required properties:
- compatible: Should be set to "fsl,imx6q-weim"
- compatible: Should be set to "fsl,<soc>-weim"
- reg: A resource specifier for the register space
(see the example below)
- clocks: the clock, see the example below.
......@@ -21,11 +21,18 @@ Required properties:
Timing property for child nodes. It is mandatory, not optional.
- fsl,weim-cs-timing: The timing array, contains 6 timing values for the
- fsl,weim-cs-timing: The timing array, contains timing values for the
child node. We can get the CS index from the child
node's "reg" property. This property contains the values
for the registers EIM_CSnGCR1, EIM_CSnGCR2, EIM_CSnRCR1,
EIM_CSnRCR2, EIM_CSnWCR1, EIM_CSnWCR2 in this order.
node's "reg" property. The number of registers depends
on the selected chip.
For i.MX1, i.MX21 ("fsl,imx1-weim") there are two
registers: CSxU, CSxL.
For i.MX25, i.MX27, i.MX31 and i.MX35 ("fsl,imx27-weim")
there are three registers: CSCRxU, CSCRxL, CSCRxA.
For i.MX50, i.MX53 ("fsl,imx50-weim"),
i.MX51 ("fsl,imx51-weim") and i.MX6Q ("fsl,imx6q-weim")
there are six registers: CSxGCR1, CSxGCR2, CSxRCR1,
CSxRCR2, CSxWCR1, CSxWCR2.
Example for an imx6q-sabreauto board, the NOR flash connected to the WEIM:
......
Documentation/devicetree/bindings/bus/mvebu-mbus.txt 0 → 100644
View file @ b4b50fd7
* Marvell MBus
Required properties:
- compatible: Should be set to one of the following:
marvell,armada370-mbus
marvell,armadaxp-mbus
marvell,armada370-mbus
marvell,armadaxp-mbus
marvell,kirkwood-mbus
marvell,dove-mbus
marvell,orion5x-88f5281-mbus
marvell,orion5x-88f5182-mbus
marvell,orion5x-88f5181-mbus
marvell,orion5x-88f6183-mbus
marvell,mv78xx0-mbus
- address-cells: Must be '2'. The first cell for the MBus ID encoding,
the second cell for the address offset within the window.
- size-cells: Must be '1'.
- ranges: Must be set up to provide a proper translation for each child.
See the examples below.
- controller: Contains a single phandle referring to the MBus controller
node. This allows to specify the node that contains the
registers that control the MBus, which is typically contained
within the internal register window (see below).
Optional properties:
- pcie-mem-aperture: This optional property contains the aperture for
the memory region of the PCIe driver.
If it's defined, it must encode the base address and
size for the address decoding windows allocated for
the PCIe memory region.
- pcie-io-aperture: Just as explained for the above property, this
optional property contains the aperture for the
I/O region of the PCIe driver.
* Marvell MBus controller
Required properties:
- compatible: Should be set to "marvell,mbus-controller".
- reg: Device's register space.
Two entries are expected (see the examples below):
the first one controls the devices decoding window and
the second one controls the SDRAM decoding window.
Example:
soc {
compatible = "marvell,armada370-mbus", "simple-bus";
#address-cells = <2>;
#size-cells = <1>;
controller = <&mbusc>;
pcie-mem-aperture = <0xe0000000 0x8000000>;
pcie-io-aperture = <0xe8000000 0x100000>;
internal-regs {
compatible = "simple-bus";
mbusc: mbus-controller@20000 {
compatible = "marvell,mbus-controller";
reg = <0x20000 0x100>, <0x20180 0x20>;
};
/* more children ...*/
};
};
** MBus address decoding window specification
The MBus children address space is comprised of two cells: the first one for
the window ID and the second one for the offset within the window.
In order to allow to describe valid and non-valid window entries, the
following encoding is used:
0xSIAA0000 0x00oooooo
Where:
S = 0x0 for a MBus valid window
S = 0xf for a non-valid window (see below)
If S = 0x0, then:
I = 4-bit window target ID
AA = windpw attribute
If S = 0xf, then:
I = don't care
AA = 1 for internal register
Following the above encoding, for each ranges entry for a MBus valid window
(S = 0x0), an address decoding window is allocated. On the other side,
entries for translation that do not correspond to valid windows (S = 0xf)
are skipped.
soc {
compatible = "marvell,armada370-mbus", "simple-bus";
#address-cells = <2>;
#size-cells = <1>;
controller = <&mbusc>;
ranges = <0xf0010000 0 0 0xd0000000 0x100000
0x01e00000 0 0 0xfff00000 0x100000>;
bootrom {
compatible = "marvell,bootrom";
reg = <0x01e00000 0 0x100000>;
};
/* other children */
...
internal-regs {
compatible = "simple-bus";
ranges = <0 0xf0010000 0 0x100000>;
mbusc: mbus-controller@20000 {
compatible = "marvell,mbus-controller";
reg = <0x20000 0x100>, <0x20180 0x20>;
};
/* more children ...*/
};
};
In the shown example, the translation entry in the 'ranges' property is what
makes the MBus driver create a static decoding window for the corresponding
given child device. Note that the binding does not require child nodes to be
present. Of course, child nodes are needed to probe the devices.
Since each window is identified by its target ID and attribute ID there's
a special macro that can be use to simplify the translation entries:
#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
Using this macro, the above example would be:
soc {
compatible = "marvell,armada370-mbus", "simple-bus";
#address-cells = <2>;
#size-cells = <1>;
controller = <&mbusc>;
ranges = < MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000
MBUS_ID(0x01, 0xe0) 0 0 0xfff00000 0x100000>;
bootrom {
compatible = "marvell,bootrom";
reg = <MBUS_ID(0x01, 0xe0) 0 0x100000>;
};
/* other children */
...
internal-regs {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
mbusc: mbus-controller@20000 {
compatible = "marvell,mbus-controller";
reg = <0x20000 0x100>, <0x20180 0x20>;
};
/* other children */
...
};
};
** About the window base address
Remember the MBus controller allows a great deal of flexibility for choosing
the decoding window base address. When planning the device tree layout it's
possible to choose any address as the base address, provided of course there's
a region large enough available, and with the required alignment.
Yet in other words: there's nothing preventing us from setting a base address
of 0xf0000000, or 0xd0000000 for the NOR device shown above, if such region is
unused.
** Window allocation policy
The mbus-node ranges property defines a set of mbus windows that are expected
to be set by the operating system and that are guaranteed to be free of overlaps
with one another or with the system memory ranges.
Each entry in the property refers to exactly one window. If the operating system
choses to use a different set of mbus windows, it must ensure that any address
translations performed from downstream devices are adapted accordingly.
The operating system may insert additional mbus windows that do not conflict
with the ones listed in the ranges, e.g. for mapping PCIe devices.
As a special case, the internal register window must be set up by the boot
loader at the address listed in the ranges property, since access to that region
is needed to set up the other windows.
** Example
See the example below, where a more complete device tree is shown:
soc {
compatible = "marvell,armadaxp-mbus", "simple-bus";
controller = <&mbusc>;
ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000 /* internal-regs */
MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x8000000>;
bootrom {
compatible = "marvell,bootrom";
reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
};
devbus-bootcs {
status = "okay";
ranges = <0 MBUS_ID(0x01, 0x2f) 0 0x8000000>;
/* NOR */
nor {
compatible = "cfi-flash";
reg = <0 0x8000000>;
bank-width = <2>;
};
};
pcie-controller {
compatible = "marvell,armada-xp-pcie";
status = "okay";
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
ranges =
<0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
0x82000800 0 0xe0000000 MBUS_ID(0x04, 0xe8) 0xe0000000 0 0x08000000 /* Port 0.0 MEM */
0x81000800 0 0 MBUS_ID(0x04, 0xe0) 0xe8000000 0 0x00100000 /* Port 0.0 IO */>;
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
};
internal-regs {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
mbusc: mbus-controller@20000 {
reg = <0x20000 0x100>, <0x20180 0x20>;
};
interrupt-controller@20000 {
reg = <0x20a00 0x2d0>, <0x21070 0x58>;
};
};
};
Documentation/devicetree/bindings/clock/imx5-clock.txt
View file @ b4b50fd7
......@@ -197,6 +197,7 @@ clocks and IDs.
spdif0_gate 183
spdif1_gate 184
spdif_ipg_gate 185
ocram 186
Examples (for mx53):
......
Documentation/devicetree/bindings/clock/imx6q-clock.txt
View file @ b4b50fd7
......@@ -209,6 +209,12 @@ clocks and IDs.
pll5_post_div 194
pll5_video_div 195
eim_slow 196
spdif 197
cko2_sel 198
cko2_podf 199
cko2 200
cko 201
vdoa 202
Examples:
......
Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt 0 → 100644
View file @ b4b50fd7
NVIDIA Tegra PCIe controller
Required properties:
- compatible: "nvidia,tegra20-pcie" or "nvidia,tegra30-pcie"
- device_type: Must be "pci"
- reg: A list of physical base address and length for each set of controller
registers. Must contain an entry for each entry in the reg-names property.
- reg-names: Must include the following entries:
"pads": PADS registers
"afi": AFI registers
"cs": configuration space region
- interrupts: A list of interrupt outputs of the controller. Must contain an
entry for each entry in the interrupt-names property.
- interrupt-names: Must include the following entries:
"intr": The Tegra interrupt that is asserted for controller interrupts
"msi": The Tegra interrupt that is asserted when an MSI is received
- pex-clk-supply: Supply voltage for internal reference clock
- vdd-supply: Power supply for controller (1.05V)
- avdd-supply: Power supply for controller (1.05V) (not required for Tegra20)
- bus-range: Range of bus numbers associated with this controller
- #address-cells: Address representation for root ports (must be 3)
- cell 0 specifies the bus and device numbers of the root port:
[23:16]: bus number
[15:11]: device number
- cell 1 denotes the upper 32 address bits and should be 0
- cell 2 contains the lower 32 address bits and is used to translate to the
CPU address space
- #size-cells: Size representation for root ports (must be 2)
- ranges: Describes the translation of addresses for root ports and standard
PCI regions. The entries must be 6 cells each, where the first three cells
correspond to the address as described for the #address-cells property
above, the fourth cell is the physical CPU address to translate to and the
fifth and six cells are as described for the #size-cells property above.
- The first two entries are expected to translate the addresses for the root
port registers, which are referenced by the assigned-addresses property of
the root port nodes (see below).
- The remaining entries setup the mapping for the standard I/O, memory and
prefetchable PCI regions. The first cell determines the type of region
that is setup:
- 0x81000000: I/O memory region
- 0x82000000: non-prefetchable memory region
- 0xc2000000: prefetchable memory region
Please refer to the standard PCI bus binding document for a more detailed
explanation.
- clocks: List of clock inputs of the controller. Must contain an entry for
each entry in the clock-names property.
- clock-names: Must include the following entries:
"pex": The Tegra clock of that name
"afi": The Tegra clock of that name
"pcie_xclk": The Tegra clock of that name
"pll_e": The Tegra clock of that name
"cml": The Tegra clock of that name (not required for Tegra20)
Root ports are defined as subnodes of the PCIe controller node.
Required properties:
- device_type: Must be "pci"
- assigned-addresses: Address and size of the port configuration registers
- reg: PCI bus address of the root port
- #address-cells: Must be 3
- #size-cells: Must be 2
- ranges: Sub-ranges distributed from the PCIe controller node. An empty
property is sufficient.
- nvidia,num-lanes: Number of lanes to use for this port. Valid combinations
are:
- Root port 0 uses 4 lanes, root port 1 is unused.
- Both root ports use 2 lanes.
Example:
SoC DTSI:
pcie-controller {
compatible = "nvidia,tegra20-pcie";
device_type = "pci";
reg = <0x80003000 0x00000800 /* PADS registers */
0x80003800 0x00000200 /* AFI registers */
0x90000000 0x10000000>; /* configuration space */
reg-names = "pads", "afi", "cs";
interrupts = <0 98 0x04 /* controller interrupt */
0 99 0x04>; /* MSI interrupt */
interrupt-names = "intr", "msi";
bus-range = <0x00 0xff>;
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x82000000 0 0x80000000 0x80000000 0 0x00001000 /* port 0 registers */
0x82000000 0 0x80001000 0x80001000 0 0x00001000 /* port 1 registers */
0x81000000 0 0 0x82000000 0 0x00010000 /* downstream I/O */
0x82000000 0 0xa0000000 0xa0000000 0 0x10000000 /* non-prefetchable memory */
0xc2000000 0 0xb0000000 0xb0000000 0 0x10000000>; /* prefetchable memory */
clocks = <&tegra_car 70>, <&tegra_car 72>, <&tegra_car 74>,
<&tegra_car 118>;
clock-names = "pex", "afi", "pcie_xclk", "pll_e";
status = "disabled";
pci@1,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x80000000 0 0x1000>;
reg = <0x000800 0 0 0 0>;
status = "disabled";
#address-cells = <3>;
#size-cells = <2>;
ranges;
nvidia,num-lanes = <2>;
};
pci@2,0 {
device_type = "pci";
assigned-addresses = <0x82001000 0 0x80001000 0 0x1000>;
reg = <0x001000 0 0 0 0>;
status = "disabled";
#address-cells = <3>;
#size-cells = <2>;
ranges;
nvidia,num-lanes = <2>;
};
};
Board DTS:
pcie-controller {
status = "okay";
vdd-supply = <&pci_vdd_reg>;
pex-clk-supply = <&pci_clk_reg>;
/* root port 00:01.0 */
pci@1,0 {
status = "okay";
/* bridge 01:00.0 (optional) */
pci@0,0 {
reg = <0x010000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
/* endpoint 02:00.0 */
pci@0,0 {
reg = <0x020000 0 0 0 0>;
};
};
};
};
Note that devices on the PCI bus are dynamically discovered using PCI's bus
enumeration and therefore don't need corresponding device nodes in DT. However
if a device on the PCI bus provides a non-probeable bus such as I2C or SPI,
device nodes need to be added in order to allow the bus' children to be
instantiated at the proper location in the operating system's device tree (as
illustrated by the optional nodes in the example above).
Documentation/devicetree/bindings/watchdog/sun4i-wdt.txt → Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt
View file @ b4b50fd7
Allwinner sun4i Watchdog timer
Allwinner SoCs Watchdog timer
Required properties:
- compatible : should be "allwinner,sun4i-wdt"
- compatible : should be "allwinner,<soc-family>-wdt", the currently supported
SoC families being sun4i and sun6i
- reg : Specifies base physical address and size of the registers.
Example:
......
MAINTAINERS
View file @ b4b50fd7
......@@ -6315,6 +6315,13 @@ F: Documentation/PCI/
F: drivers/pci/
F: include/linux/pci*
PCI DRIVER FOR NVIDIA TEGRA
M: Thierry Reding <thierry.reding@gmail.com>
L: linux-tegra@vger.kernel.org
S: Supported
F: Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt
F: drivers/pci/host/pci-tegra.c
PCMCIA SUBSYSTEM
P: Linux PCMCIA Team
L: linux-pcmcia@lists.infradead.org
......
arch/arm/Kconfig
View file @ b4b50fd7
......@@ -442,7 +442,6 @@ config ARCH_NETX
config ARCH_IOP13XX
bool "IOP13xx-based"
depends on MMU
select ARCH_SUPPORTS_MSI
select CPU_XSC3
select NEED_MACH_MEMORY_H
select NEED_RET_TO_USER
......@@ -1600,7 +1599,7 @@ config ARM_PSCI
config ARCH_NR_GPIO
int
default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5
default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || SOC_DRA7XX
default 392 if ARCH_U8500
default 352 if ARCH_VT8500
default 288 if ARCH_SUNXI
......
arch/arm/boot/dts/Makefile
View file @ b4b50fd7
......@@ -91,6 +91,7 @@ dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-cloudbox.dtb \
kirkwood-ns2max.dtb \
kirkwood-ns2mini.dtb \
kirkwood-nsa310.dtb \
kirkwood-nsa310a.dtb \
kirkwood-sheevaplug.dtb \
kirkwood-sheevaplug-esata.dtb \
kirkwood-topkick.dtb \
......@@ -102,7 +103,9 @@ dtb-$(CONFIG_ARCH_MSM) += msm8660-surf.dtb \
msm8960-cdp.dtb
dtb-$(CONFIG_ARCH_MVEBU) += armada-370-db.dtb \
armada-370-mirabox.dtb \
armada-370-netgear-rn102.dtb \
armada-370-rd.dtb \
armada-xp-axpwifiap.dtb \
armada-xp-db.dtb \
armada-xp-gp.dtb \
armada-xp-openblocks-ax3-4.dtb
......@@ -114,6 +117,8 @@ dtb-$(CONFIG_ARCH_MXC) += \
imx27-pdk.dtb \
imx27-phytec-phycore-som.dtb \
imx27-phytec-phycore-rdk.dtb \
imx27-phytec-phycard-s-som.dtb \
imx27-phytec-phycard-s-rdk.dtb \
imx31-bug.dtb \
imx51-apf51.dtb \
imx51-apf51dev.dtb \
......@@ -133,6 +138,7 @@ dtb-$(CONFIG_ARCH_MXC) += \
imx6q-sabrelite.dtb \
imx6q-sabresd.dtb \
imx6q-sbc6x.dtb \
imx6q-wandboard.dtb \
imx6sl-evk.dtb \
vf610-twr.dtb
dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \
......
arch/arm/boot/dts/armada-370-db.dts
View file @ b4b50fd7
......@@ -14,7 +14,7 @@
*/
/dts-v1/;
/include/ "armada-370.dtsi"
#include "armada-370.dtsi"
/ {
model = "Marvell Armada 370 Evaluation Board";
......@@ -30,6 +30,9 @@ memory {
};
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000
MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
internal-regs {
serial@12000 {
clock-frequency = <200000000>;
......
arch/arm/boot/dts/armada-370-mirabox.dts
View file @ b4b50fd7
......@@ -9,7 +9,7 @@
*/
/dts-v1/;
/include/ "armada-370.dtsi"
#include "armada-370.dtsi"
/ {
model = "Globalscale Mirabox";
......@@ -25,6 +25,25 @@ memory {
};
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000
MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
pcie-controller {
status = "okay";
/* Internal mini-PCIe connector */
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
/* Connected on the PCB to a USB 3.0 XHCI controller */
pcie@2,0 {
/* Port 1, Lane 0 */
status = "okay";
};
};
internal-regs {
serial@12000 {
clock-frequency = <200000000>;
......@@ -120,22 +139,6 @@ pca9505: pca9505@25 {
reg = <0x25>;
};
};
pcie-controller {
status = "okay";
/* Internal mini-PCIe connector */
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
/* Connected on the PCB to a USB 3.0 XHCI controller */
pcie@2,0 {
/* Port 1, Lane 0 */
status = "okay";
};
};
};
};
};
arch/arm/boot/dts/armada-370-netgear-rn102.dts 0 → 100644
View file @ b4b50fd7
/*
* Device Tree file for NETGEAR ReadyNAS 102
*
* Copyright (C) 2013, Arnaud EBALARD <arno@natisbad.org>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*/
/dts-v1/;
#include "armada-370.dtsi"
/ {
model = "NETGEAR ReadyNAS 102";
compatible = "netgear,readynas-102", "marvell,armada370", "marvell,armada-370-xp";
chosen {
bootargs = "console=ttyS0,115200 earlyprintk";
};
memory {
device_type = "memory";
reg = <0x00000000 0x20000000>; /* 512 MB */
};
soc {
internal-regs {
serial@12000 {
clock-frequency = <200000000>;
status = "okay";
};
sata@a0000 {
nr-ports = <2>;
status = "okay";
};
pinctrl {
power_led_pin: power-led-pin {
marvell,pins = "mpp57";
marvell,function = "gpio";
};
sata1_led_pin: sata1-led-pin {
marvell,pins = "mpp15";
marvell,function = "gpio";
};
sata2_led_pin: sata2-led-pin {
marvell,pins = "mpp14";
marvell,function = "gpio";
};
backup_led_pin: backup-led-pin {
marvell,pins = "mpp56";
marvell,function = "gpio";
};
};
mdio {
phy0: ethernet-phy@0 {
reg = <0>;
};
};
ethernet@74000 {
status = "okay";
phy = <&phy0>;
phy-mode = "rgmii-id";
};
usb@50000 {
status = "okay";
};
i2c@11000 {
compatible = "marvell,mv64xxx-i2c";
clock-frequency = <100000>;
status = "okay";
g762: g762@3e {
compatible = "gmt,g762";
reg = <0x3e>;
clocks = <&g762_clk>; /* input clock */
fan_gear_mode = <0>;
fan_startv = <1>;
pwm_polarity = <0>;
};
};
pcie-controller {
status = "okay";
/* Connected to Marvell SATA controller */
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
/* Connected to FL1009 USB 3.0 controller */
pcie@2,0 {
/* Port 1, Lane 0 */
status = "okay";
};
};
};
};
clocks {
#address-cells = <1>;
#size-cells = <0>;
g762_clk: fixedclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <8192>;
};
};
gpio_leds {
compatible = "gpio-leds";
pinctrl-0 = < &power_led_pin
&sata1_led_pin
&sata2_led_pin
&backup_led_pin >;
pinctrl-names = "default";
blue_power_led {
label = "rn102:blue:pwr";
gpios = <&gpio1 25 1>; /* GPIO 57 Active Low */
linux,default-trigger = "heartbeat";
};
green_sata1_led {
label = "rn102:green:sata1";
gpios = <&gpio0 15 1>; /* GPIO 15 Active Low */
default-state = "on";
};
green_sata2_led {
label = "rn102:green:sata2";
gpios = <&gpio0 14 1>; /* GPIO 14 Active Low */
default-state = "on";
};
green_backup_led {
label = "rn102:green:backup";
gpios = <&gpio1 24 1>; /* GPIO 56 Active Low */
default-state = "on";
};
};
gpio_keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
button@1 {
label = "Power Button";
linux,code = <116>; /* KEY_POWER */
gpios = <&gpio1 30 1>;
};
button@2 {
label = "Reset Button";
linux,code = <0x198>; /* KEY_RESTART */
gpios = <&gpio0 6 1>;
};
button@3 {
label = "Backup Button";
linux,code = <133>; /* KEY_COPY */
gpios = <&gpio1 26 1>;
};
};
};
arch/arm/boot/dts/armada-370-rd.dts
View file @ b4b50fd7
......@@ -12,7 +12,7 @@
*/
/dts-v1/;
/include/ "armada-370.dtsi"
#include "armada-370.dtsi"
/ {
model = "Marvell Armada 370 Reference Design";
......@@ -28,6 +28,25 @@ memory {
};
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000
MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
pcie-controller {
status = "okay";
/* Internal mini-PCIe connector */
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
/* Internal mini-PCIe connector */
pcie@2,0 {
/* Port 1, Lane 0 */
status = "okay";
};
};
internal-regs {
serial@12000 {
clock-frequency = <200000000>;
......@@ -85,22 +104,6 @@ button@1 {
gpios = <&gpio0 6 1>;
};
};
pcie-controller {
status = "okay";
/* Internal mini-PCIe connector */
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
/* Internal mini-PCIe connector */
pcie@2,0 {
/* Port 1, Lane 0 */
status = "okay";
};
};
};
};
};
arch/arm/boot/dts/armada-370-xp.dtsi
View file @ b4b50fd7
......@@ -18,6 +18,8 @@
/include/ "skeleton64.dtsi"
#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
/ {
model = "Marvell Armada 370 and XP SoC";
compatible = "marvell,armada-370-xp";
......@@ -38,18 +40,73 @@ cpu@0 {
};
soc {
#address-cells = <1>;
#address-cells = <2>;
#size-cells = <1>;
compatible = "simple-bus";
controller = <&mbusc>;
interrupt-parent = <&mpic>;
ranges = <0 0 0xd0000000 0x0100000 /* internal registers */
0xe0000000 0 0xe0000000 0x8100000 /* PCIe */>;
pcie-mem-aperture = <0xe0000000 0x8000000>;
pcie-io-aperture = <0xe8000000 0x100000>;
devbus-bootcs {
compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&coreclk 0>;
status = "disabled";
};
devbus-cs0 {
compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&coreclk 0>;
status = "disabled";
};
devbus-cs1 {
compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&coreclk 0>;
status = "disabled";
};
devbus-cs2 {
compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&coreclk 0>;
status = "disabled";
};
devbus-cs3 {
compatible = "marvell,mvebu-devbus";
reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&coreclk 0>;
status = "disabled";
};
internal-regs {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
mbusc: mbus-controller@20000 {
compatible = "marvell,mbus-controller";
reg = <0x20000 0x100>, <0x20180 0x20>;
};
mpic: interrupt-controller@20000 {
compatible = "marvell,mpic";
......@@ -81,10 +138,8 @@ serial@12100 {
};
timer@20300 {
compatible = "marvell,armada-370-xp-timer";
reg = <0x20300 0x30>, <0x21040 0x30>;
interrupts = <37>, <38>, <39>, <40>, <5>, <6>;
clocks = <&coreclk 2>;
};
sata@a0000 {
......@@ -195,50 +250,6 @@ spi1: spi@10680 {
status = "disabled";
};
devbus-bootcs@10400 {
compatible = "marvell,mvebu-devbus";
reg = <0x10400 0x8>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&coreclk 0>;
status = "disabled";
};
devbus-cs0@10408 {
compatible = "marvell,mvebu-devbus";
reg = <0x10408 0x8>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&coreclk 0>;
status = "disabled";
};
devbus-cs1@10410 {
compatible = "marvell,mvebu-devbus";
reg = <0x10410 0x8>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&coreclk 0>;
status = "disabled";
};
devbus-cs2@10418 {
compatible = "marvell,mvebu-devbus";
reg = <0x10418 0x8>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&coreclk 0>;
status = "disabled";
};
devbus-cs3@10420 {
compatible = "marvell,mvebu-devbus";
reg = <0x10420 0x8>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&coreclk 0>;
status = "disabled";
};
};
};
};
arch/arm/boot/dts/armada-370.dtsi
View file @ b4b50fd7
......@@ -15,7 +15,7 @@
* common to all Armada SoCs.
*/
/include/ "armada-370-xp.dtsi"
#include "armada-370-xp.dtsi"
/include/ "skeleton.dtsi"
/ {
......@@ -29,8 +29,66 @@ aliases {
};
soc {
ranges = <0 0xd0000000 0x0100000 /* internal registers */
0xe0000000 0xe0000000 0x8100000 /* PCIe */>;
compatible = "marvell,armada370-mbus", "simple-bus";
bootrom {
compatible = "marvell,bootrom";
reg = <MBUS_ID(0x01, 0xe0) 0 0x100000>;
};
pcie-controller {
compatible = "marvell,armada-370-pcie";
status = "disabled";
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
bus-range = <0x00 0xff>;
ranges =
<0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
0x82000000 0x2 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
0x81000000 0x2 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */>;
pcie@1,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
reg = <0x0800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
0x81000000 0 0 0x81000000 0x1 0 1 0>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 58>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 5>;
status = "disabled";
};
pcie@2,0 {
device_type = "pci";
assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
reg = <0x1000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
0x81000000 0 0 0x81000000 0x2 0 1 0>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 62>;
marvell,pcie-port = <1>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 9>;
status = "disabled";
};
};
internal-regs {
system-controller@18200 {
compatible = "marvell,armada-370-xp-system-controller";
......@@ -78,7 +136,7 @@ gpio0: gpio@18100 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupts-cells = <2>;
#interrupt-cells = <2>;
interrupts = <82>, <83>, <84>, <85>;
};
......@@ -89,7 +147,7 @@ gpio1: gpio@18140 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupts-cells = <2>;
#interrupt-cells = <2>;
interrupts = <87>, <88>, <89>, <90>;
};
......@@ -100,10 +158,15 @@ gpio2: gpio@18180 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupts-cells = <2>;
#interrupt-cells = <2>;
interrupts = <91>;
};
timer@20300 {
compatible = "marvell,armada-370-timer";
clocks = <&coreclk 2>;
};
coreclk: mvebu-sar@18230 {
compatible = "marvell,armada-370-core-clock";
reg = <0x18230 0x08>;
......@@ -169,54 +232,6 @@ thermal@18300 {
0x18304 0x4>;
status = "okay";
};
pcie-controller {
compatible = "marvell,armada-370-pcie";
status = "disabled";
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
bus-range = <0x00 0xff>;
ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */
0x82000000 0 0x80000 0x80000 0 0x00002000 /* Port 1.0 registers */
0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
pcie@1,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
reg = <0x0800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 58>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 5>;
status = "disabled";
};
pcie@2,0 {
device_type = "pci";
assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
reg = <0x1000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 62>;
marvell,pcie-port = <1>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 9>;
status = "disabled";
};
};
};
};
};
arch/arm/boot/dts/armada-xp-axpwifiap.dts 0 → 100644
View file @ b4b50fd7
/*
* Device Tree file for Marvell RD-AXPWiFiAP.
*
* Note: this board is shipped with a new generation boot loader that
* remaps internal registers at 0xf1000000. Therefore, if earlyprintk
* is used, the CONFIG_DEBUG_MVEBU_UART_ALTERNATE option should be
* used.
*
* Copyright (C) 2013 Marvell
*
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
/dts-v1/;
#include "armada-xp-mv78230.dtsi"
/ {
model = "Marvell RD-AXPWiFiAP";
compatible = "marvell,rd-axpwifiap", "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp";
chosen {
bootargs = "console=ttyS0,115200 earlyprintk";
};
memory {
device_type = "memory";
reg = <0x00000000 0x00000000 0x00000000 0x40000000>; /* 1GB */
};
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>;
pcie-controller {
status = "okay";
/* First mini-PCIe port */
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
/* Second mini-PCIe port */
pcie@2,0 {
/* Port 0, Lane 1 */
status = "okay";
};
/* Renesas uPD720202 USB 3.0 controller */
pcie@3,0 {
/* Port 0, Lane 3 */
status = "okay";
};
};
internal-regs {
pinctrl {
pinctrl-0 = <&pmx_phy_int>;
pinctrl-names = "default";
pmx_ge0: pmx-ge0 {
marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3",
"mpp4", "mpp5", "mpp6", "mpp7",
"mpp8", "mpp9", "mpp10", "mpp11";
marvell,function = "ge0";
};
pmx_ge1: pmx-ge1 {
marvell,pins = "mpp12", "mpp13", "mpp14", "mpp15",
"mpp16", "mpp17", "mpp18", "mpp19",
"mpp20", "mpp21", "mpp22", "mpp23";
marvell,function = "ge1";
};
pmx_keys: pmx-keys {
marvell,pins = "mpp33";
marvell,function = "gpio";
};
pmx_spi: pmx-spi {
marvell,pins = "mpp36", "mpp37", "mpp38", "mpp39";
marvell,function = "spi";
};
pmx_phy_int: pmx-phy-int {
marvell,pins = "mpp32";
marvell,function = "gpio";
};
};
serial@12000 {
clock-frequency = <250000000>;
status = "okay";
};
serial@12100 {
clock-frequency = <250000000>;
status = "okay";
};
sata@a0000 {
nr-ports = <1>;
status = "okay";
};
mdio {
phy0: ethernet-phy@0 {
reg = <0>;
};
phy1: ethernet-phy@1 {
reg = <1>;
};
};
ethernet@70000 {
pinctrl-0 = <&pmx_ge0>;
pinctrl-names = "default";
status = "okay";
phy = <&phy0>;
phy-mode = "rgmii-id";
};
ethernet@74000 {
pinctrl-0 = <&pmx_ge1>;
pinctrl-names = "default";
status = "okay";
phy = <&phy1>;
phy-mode = "rgmii-id";
};
spi0: spi@10600 {
status = "okay";
pinctrl-0 = <&pmx_spi>;
pinctrl-names = "default";
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "n25q128a13";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <108000000>;
};
};
};
};
gpio_keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
pinctrl-0 = <&pmx_keys>;
pinctrl-names = "default";
button@1 {
label = "Factory Reset Button";
linux,code = <141>; /* KEY_SETUP */
gpios = <&gpio1 1 1>;
};
};
};
arch/arm/boot/dts/armada-xp-db.dts
View file @ b4b50fd7
......@@ -14,7 +14,7 @@
*/
/dts-v1/;
/include/ "armada-xp-mv78460.dtsi"
#include "armada-xp-mv78460.dtsi"
/ {
model = "Marvell Armada XP Evaluation Board";
......@@ -30,9 +30,70 @@ memory {
};
soc {
ranges = <0 0 0xd0000000 0x100000 /* Internal registers 1MiB */
0xe0000000 0 0xe0000000 0x8100000 /* PCIe */
0xf0000000 0 0xf0000000 0x1000000>; /* Device Bus, NOR 16MiB */
ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000
MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000>;
devbus-bootcs {
status = "okay";
/* Device Bus parameters are required */
/* Read parameters */
devbus,bus-width = <8>;
devbus,turn-off-ps = <60000>;
devbus,badr-skew-ps = <0>;
devbus,acc-first-ps = <124000>;
devbus,acc-next-ps = <248000>;
devbus,rd-setup-ps = <0>;
devbus,rd-hold-ps = <0>;
/* Write parameters */
devbus,sync-enable = <0>;
devbus,wr-high-ps = <60000>;
devbus,wr-low-ps = <60000>;
devbus,ale-wr-ps = <60000>;
/* NOR 16 MiB */
nor@0 {
compatible = "cfi-flash";
reg = <0 0x1000000>;
bank-width = <2>;
};
};
pcie-controller {
status = "okay";
/*
* All 6 slots are physically present as
* standard PCIe slots on the board.
*/
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
pcie@2,0 {
/* Port 0, Lane 1 */
status = "okay";
};
pcie@3,0 {
/* Port 0, Lane 2 */
status = "okay";
};
pcie@4,0 {
/* Port 0, Lane 3 */
status = "okay";
};
pcie@9,0 {
/* Port 2, Lane 0 */
status = "okay";
};
pcie@10,0 {
/* Port 3, Lane 0 */
status = "okay";
};
};
internal-regs {
serial@12000 {
......@@ -127,68 +188,6 @@ spi-flash@0 {
spi-max-frequency = <20000000>;
};
};
pcie-controller {
status = "okay";
/*
* All 6 slots are physically present as
* standard PCIe slots on the board.
*/
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
pcie@2,0 {
/* Port 0, Lane 1 */
status = "okay";
};
pcie@3,0 {
/* Port 0, Lane 2 */
status = "okay";
};
pcie@4,0 {
/* Port 0, Lane 3 */
status = "okay";
};
pcie@9,0 {
/* Port 2, Lane 0 */
status = "okay";
};
pcie@10,0 {
/* Port 3, Lane 0 */
status = "okay";
};
};
devbus-bootcs@10400 {
status = "okay";
ranges = <0 0xf0000000 0x1000000>;
/* Device Bus parameters are required */
/* Read parameters */
devbus,bus-width = <8>;
devbus,turn-off-ps = <60000>;
devbus,badr-skew-ps = <0>;
devbus,acc-first-ps = <124000>;
devbus,acc-next-ps = <248000>;
devbus,rd-setup-ps = <0>;
devbus,rd-hold-ps = <0>;
/* Write parameters */
devbus,sync-enable = <0>;
devbus,wr-high-ps = <60000>;
devbus,wr-low-ps = <60000>;
devbus,ale-wr-ps = <60000>;
/* NOR 16 MiB */
nor@0 {
compatible = "cfi-flash";
reg = <0 0x1000000>;
bank-width = <2>;
};
};
};
};
};
arch/arm/boot/dts/armada-xp-gp.dts
View file @ b4b50fd7
......@@ -14,7 +14,7 @@
*/
/dts-v1/;
/include/ "armada-xp-mv78460.dtsi"
#include "armada-xp-mv78460.dtsi"
/ {
model = "Marvell Armada XP Development Board DB-MV784MP-GP";
......@@ -39,9 +39,58 @@ memory {
};
soc {
ranges = <0 0 0xd0000000 0x100000 /* Internal registers 1MiB */
0xe0000000 0 0xe0000000 0x8100000 /* PCIe */
0xf0000000 0 0xf0000000 0x1000000 /* Device Bus, NOR 16MiB */>;
ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000
MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000>;
devbus-bootcs {
status = "okay";
/* Device Bus parameters are required */
/* Read parameters */
devbus,bus-width = <8>;
devbus,turn-off-ps = <60000>;
devbus,badr-skew-ps = <0>;
devbus,acc-first-ps = <124000>;
devbus,acc-next-ps = <248000>;
devbus,rd-setup-ps = <0>;
devbus,rd-hold-ps = <0>;
/* Write parameters */
devbus,sync-enable = <0>;
devbus,wr-high-ps = <60000>;
devbus,wr-low-ps = <60000>;
devbus,ale-wr-ps = <60000>;
/* NOR 16 MiB */
nor@0 {
compatible = "cfi-flash";
reg = <0 0x1000000>;
bank-width = <2>;
};
};
pcie-controller {
status = "okay";
/*
* The 3 slots are physically present as
* standard PCIe slots on the board.
*/
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
pcie@9,0 {
/* Port 2, Lane 0 */
status = "okay";
};
pcie@10,0 {
/* Port 3, Lane 0 */
status = "okay";
};
};
internal-regs {
serial@12000 {
......@@ -126,56 +175,6 @@ spi-flash@0 {
spi-max-frequency = <108000000>;
};
};
devbus-bootcs@10400 {
status = "okay";
ranges = <0 0xf0000000 0x1000000>; /* @addr 0xf000000, size 0x1000000 */
/* Device Bus parameters are required */
/* Read parameters */
devbus,bus-width = <8>;
devbus,turn-off-ps = <60000>;
devbus,badr-skew-ps = <0>;
devbus,acc-first-ps = <124000>;
devbus,acc-next-ps = <248000>;
devbus,rd-setup-ps = <0>;
devbus,rd-hold-ps = <0>;
/* Write parameters */
devbus,sync-enable = <0>;
devbus,wr-high-ps = <60000>;
devbus,wr-low-ps = <60000>;
devbus,ale-wr-ps = <60000>;
/* NOR 16 MiB */
nor@0 {
compatible = "cfi-flash";
reg = <0 0x1000000>;
bank-width = <2>;
};
};
pcie-controller {
status = "okay";
/*
* The 3 slots are physically present as
* standard PCIe slots on the board.
*/
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
pcie@9,0 {
/* Port 2, Lane 0 */
status = "okay";
};
pcie@10,0 {
/* Port 3, Lane 0 */
status = "okay";
};
};
};
};
};
arch/arm/boot/dts/armada-xp-mv78230.dtsi
View file @ b4b50fd7
......@@ -13,7 +13,7 @@
* common to all Armada XP SoCs.
*/
/include/ "armada-xp.dtsi"
#include "armada-xp.dtsi"
/ {
model = "Marvell Armada XP MV78230 SoC";
......@@ -44,6 +44,124 @@ cpu@1 {
};
soc {
/*
* MV78230 has 2 PCIe units Gen2.0: One unit can be
* configured as x4 or quad x1 lanes. One unit is
* x4/x1.
*/
pcie-controller {
compatible = "marvell,armada-xp-pcie";
status = "disabled";
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
bus-range = <0x00 0xff>;
ranges =
<0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */
0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */>;
pcie@1,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
reg = <0x0800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
0x81000000 0 0 0x81000000 0x1 0 1 0>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 58>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 5>;
status = "disabled";
};
pcie@2,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
reg = <0x1000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
0x81000000 0 0 0x81000000 0x2 0 1 0>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 59>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <1>;
clocks = <&gateclk 6>;
status = "disabled";
};
pcie@3,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
reg = <0x1800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
0x81000000 0 0 0x81000000 0x3 0 1 0>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 60>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <2>;
clocks = <&gateclk 7>;
status = "disabled";
};
pcie@4,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
reg = <0x2000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
0x81000000 0 0 0x81000000 0x4 0 1 0>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 61>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <3>;
clocks = <&gateclk 8>;
status = "disabled";
};
pcie@9,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
reg = <0x4800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
0x81000000 0 0 0x81000000 0x9 0 1 0>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 99>;
marvell,pcie-port = <2>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 26>;
status = "disabled";
};
};
internal-regs {
pinctrl {
compatible = "marvell,mv78230-pinctrl";
......@@ -63,7 +181,7 @@ gpio0: gpio@18100 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupts-cells = <2>;
#interrupt-cells = <2>;
interrupts = <82>, <83>, <84>, <85>;
};
......@@ -74,113 +192,9 @@ gpio1: gpio@18140 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupts-cells = <2>;
#interrupt-cells = <2>;
interrupts = <87>, <88>, <89>;
};
/*
* MV78230 has 2 PCIe units Gen2.0: One unit can be
* configured as x4 or quad x1 lanes. One unit is
* x4/x1.
*/
pcie-controller {
compatible = "marvell,armada-xp-pcie";
status = "disabled";
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
bus-range = <0x00 0xff>;
ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */
0x82000000 0 0x42000 0x42000 0 0x00002000 /* Port 2.0 registers */
0x82000000 0 0x44000 0x44000 0 0x00002000 /* Port 0.1 registers */
0x82000000 0 0x48000 0x48000 0 0x00002000 /* Port 0.2 registers */
0x82000000 0 0x4c000 0x4c000 0 0x00002000 /* Port 0.3 registers */
0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
pcie@1,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
reg = <0x0800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 58>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 5>;
status = "disabled";
};
pcie@2,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
reg = <0x1000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 59>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <1>;
clocks = <&gateclk 6>;
status = "disabled";
};
pcie@3,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
reg = <0x1800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 60>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <2>;
clocks = <&gateclk 7>;
status = "disabled";
};
pcie@4,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
reg = <0x2000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 61>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <3>;
clocks = <&gateclk 8>;
status = "disabled";
};
pcie@9,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
reg = <0x4800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 99>;
marvell,pcie-port = <2>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 26>;
status = "disabled";
};
};
};
};
};
arch/arm/boot/dts/armada-xp-mv78260.dtsi
View file @ b4b50fd7
......@@ -13,7 +13,7 @@
* common to all Armada XP SoCs.
*/
/include/ "armada-xp.dtsi"
#include "armada-xp.dtsi"
/ {
model = "Marvell Armada XP MV78260 SoC";
......@@ -45,6 +45,145 @@ cpu@1 {
};
soc {
/*
* MV78260 has 3 PCIe units Gen2.0: Two units can be
* configured as x4 or quad x1 lanes. One unit is
* x4/x1.
*/
pcie-controller {
compatible = "marvell,armada-xp-pcie";
status = "disabled";
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
bus-range = <0x00 0xff>;
ranges =
<0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000 /* Port 3.0 registers */
0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */
0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
0x82000000 0x9 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
0x81000000 0x9 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */
0x82000000 0xa 0 MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */
0x81000000 0xa 0 MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO */>;
pcie@1,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
reg = <0x0800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
0x81000000 0 0 0x81000000 0x1 0 1 0>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 58>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 5>;
status = "disabled";
};
pcie@2,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
reg = <0x1000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
0x81000000 0 0 0x81000000 0x2 0 1 0>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 59>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <1>;
clocks = <&gateclk 6>;
status = "disabled";
};
pcie@3,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
reg = <0x1800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
0x81000000 0 0 0x81000000 0x3 0 1 0>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 60>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <2>;
clocks = <&gateclk 7>;
status = "disabled";
};
pcie@4,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
reg = <0x2000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
0x81000000 0 0 0x81000000 0x4 0 1 0>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 61>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <3>;
clocks = <&gateclk 8>;
status = "disabled";
};
pcie@9,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
reg = <0x4800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
0x81000000 0 0 0x81000000 0x9 0 1 0>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 99>;
marvell,pcie-port = <2>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 26>;
status = "disabled";
};
pcie@10,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x82000 0 0x2000>;
reg = <0x5000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0
0x81000000 0 0 0x81000000 0xa 0 1 0>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 103>;
marvell,pcie-port = <3>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 27>;
status = "disabled";
};
};
internal-regs {
pinctrl {
compatible = "marvell,mv78260-pinctrl";
......@@ -64,7 +203,7 @@ gpio0: gpio@18100 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupts-cells = <2>;
#interrupt-cells = <2>;
interrupts = <82>, <83>, <84>, <85>;
};
......@@ -75,7 +214,7 @@ gpio1: gpio@18140 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupts-cells = <2>;
#interrupt-cells = <2>;
interrupts = <87>, <88>, <89>, <90>;
};
......@@ -86,7 +225,7 @@ gpio2: gpio@18180 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupts-cells = <2>;
#interrupt-cells = <2>;
interrupts = <91>;
};
......@@ -97,128 +236,6 @@ ethernet@34000 {
clocks = <&gateclk 1>;
status = "disabled";
};
/*
* MV78260 has 3 PCIe units Gen2.0: Two units can be
* configured as x4 or quad x1 lanes. One unit is
* x4/x1.
*/
pcie-controller {
compatible = "marvell,armada-xp-pcie";
status = "disabled";
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
bus-range = <0x00 0xff>;
ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */
0x82000000 0 0x42000 0x42000 0 0x00002000 /* Port 2.0 registers */
0x82000000 0 0x44000 0x44000 0 0x00002000 /* Port 0.1 registers */
0x82000000 0 0x48000 0x48000 0 0x00002000 /* Port 0.2 registers */
0x82000000 0 0x4c000 0x4c000 0 0x00002000 /* Port 0.3 registers */
0x82000000 0 0x80000 0x80000 0 0x00002000 /* Port 1.0 registers */
0x82000000 0 0x82000 0x82000 0 0x00002000 /* Port 3.0 registers */
0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
pcie@1,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
reg = <0x0800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 58>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 5>;
status = "disabled";
};
pcie@2,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
reg = <0x1000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 59>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <1>;
clocks = <&gateclk 6>;
status = "disabled";
};
pcie@3,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
reg = <0x1800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 60>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <2>;
clocks = <&gateclk 7>;
status = "disabled";
};
pcie@4,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
reg = <0x2000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 61>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <3>;
clocks = <&gateclk 8>;
status = "disabled";
};
pcie@9,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
reg = <0x4800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 99>;
marvell,pcie-port = <2>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 26>;
status = "disabled";
};
pcie@10,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x82000 0 0x2000>;
reg = <0x5000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 103>;
marvell,pcie-port = <3>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 27>;
status = "disabled";
};
};
};
};
};
arch/arm/boot/dts/armada-xp-mv78460.dtsi
View file @ b4b50fd7
This diff is collapsed.
arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
View file @ b4b50fd7
......@@ -11,7 +11,7 @@
*/
/dts-v1/;
/include/ "armada-xp-mv78260.dtsi"
#include "armada-xp-mv78260.dtsi"
/ {
model = "PlatHome OpenBlocks AX3-4 board";
......@@ -27,9 +27,46 @@ memory {
};
soc {
ranges = <0 0 0xd0000000 0x100000 /* Internal registers 1MiB */
0xe0000000 0 0xe0000000 0x8100000 /* PCIe */
0xf0000000 0 0xf0000000 0x8000000 /* Device Bus, NOR 128MiB */>;
ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000
MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x8000000>;
devbus-bootcs {
status = "okay";
/* Device Bus parameters are required */
/* Read parameters */
devbus,bus-width = <8>;
devbus,turn-off-ps = <60000>;
devbus,badr-skew-ps = <0>;
devbus,acc-first-ps = <124000>;
devbus,acc-next-ps = <248000>;
devbus,rd-setup-ps = <0>;
devbus,rd-hold-ps = <0>;
/* Write parameters */
devbus,sync-enable = <0>;
devbus,wr-high-ps = <60000>;
devbus,wr-low-ps = <60000>;
devbus,ale-wr-ps = <60000>;
/* NOR 128 MiB */
nor@0 {
compatible = "cfi-flash";
reg = <0 0x8000000>;
bank-width = <2>;
};
};
pcie-controller {
status = "okay";
/* Internal mini-PCIe connector */
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
};
internal-regs {
serial@12000 {
......@@ -148,49 +185,6 @@ usb@50000 {
usb@51000 {
status = "okay";
};
/* USB interface in the mini-PCIe connector */
usb@52000 {
status = "okay";
};
devbus-bootcs@10400 {
status = "okay";
ranges = <0 0xf0000000 0x8000000>; /* @addr 0xf000000, size 0x8000000 */
/* Device Bus parameters are required */
/* Read parameters */
devbus,bus-width = <8>;
devbus,turn-off-ps = <60000>;
devbus,badr-skew-ps = <0>;
devbus,acc-first-ps = <124000>;
devbus,acc-next-ps = <248000>;
devbus,rd-setup-ps = <0>;
devbus,rd-hold-ps = <0>;
/* Write parameters */
devbus,sync-enable = <0>;
devbus,wr-high-ps = <60000>;
devbus,wr-low-ps = <60000>;
devbus,ale-wr-ps = <60000>;
/* NOR 128 MiB */
nor@0 {
compatible = "cfi-flash";
reg = <0 0x8000000>;
bank-width = <2>;
};
};
pcie-controller {
status = "okay";
/* Internal mini-PCIe connector */
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
};
};
};
};
arch/arm/boot/dts/armada-xp.dtsi
View file @ b4b50fd7
......@@ -16,7 +16,7 @@
* common to all Armada SoCs.
*/
/include/ "armada-370-xp.dtsi"
#include "armada-370-xp.dtsi"
/ {
model = "Marvell Armada XP family SoC";
......@@ -27,6 +27,13 @@ aliases {
};
soc {
compatible = "marvell,armadaxp-mbus", "simple-bus";
bootrom {
compatible = "marvell,bootrom";
reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
};
internal-regs {
L2: l2-cache {
compatible = "marvell,aurora-system-cache";
......@@ -62,7 +69,7 @@ serial@12300 {
};
timer@20300 {
marvell,timer-25Mhz;
compatible = "marvell,armada-xp-timer";
};
coreclk: mvebu-sar@18230 {
......
arch/arm/boot/dts/da850-evm.dts
View file @ b4b50fd7
......@@ -90,6 +90,17 @@ partition@5 {
};
};
};
mdio: mdio@1e24000 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mdio_pins>;
bus_freq = <2200000>;
};
eth0: ethernet@1e20000 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mii_pins>;
};
};
nand_cs3@62000000 {
status = "okay";
......
arch/arm/boot/dts/da850.dtsi
View file @ b4b50fd7
......@@ -125,11 +125,33 @@ spi1_cs0_pin: pinmux_spi1_cs0 {
0x14 0x00000010 0x000000f0
>;
};
mdio_pins: pinmux_mdio_pins {
pinctrl-single,bits = <
/* MDIO_CLK, MDIO_D */
0x10 0x00000088 0x000000ff
>;
};
mii_pins: pinmux_mii_pins {
pinctrl-single,bits = <
/*
* MII_TXEN, MII_TXCLK, MII_COL
* MII_TXD_3, MII_TXD_2, MII_TXD_1
* MII_TXD_0
*/
0x8 0x88888880 0xfffffff0
/*
* MII_RXER, MII_CRS, MII_RXCLK
* MII_RXDV, MII_RXD_3, MII_RXD_2
* MII_RXD_1, MII_RXD_0
*/
0xc 0x88888888 0xffffffff
>;
};
};
serial0: serial@1c42000 {
compatible = "ns16550a";
reg = <0x42000 0x100>;
clock-frequency = <150000000>;
reg-shift = <2>;
interrupts = <25>;
status = "disabled";
......@@ -137,7 +159,6 @@ serial0: serial@1c42000 {
serial1: serial@1d0c000 {
compatible = "ns16550a";
reg = <0x10c000 0x100>;
clock-frequency = <150000000>;
reg-shift = <2>;
interrupts = <53>;
status = "disabled";
......@@ -145,7 +166,6 @@ serial1: serial@1d0c000 {
serial2: serial@1d0d000 {
compatible = "ns16550a";
reg = <0x10d000 0x100>;
clock-frequency = <150000000>;
reg-shift = <2>;
interrupts = <61>;
status = "disabled";
......@@ -216,6 +236,26 @@ spi1: spi@1f0e000 {
interrupts = <56>;
status = "disabled";
};
mdio: mdio@1e24000 {
compatible = "ti,davinci_mdio";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x224000 0x1000>;
};
eth0: ethernet@1e20000 {
compatible = "ti,davinci-dm6467-emac";
reg = <0x220000 0x4000>;
ti,davinci-ctrl-reg-offset = <0x3000>;
ti,davinci-ctrl-mod-reg-offset = <0x2000>;
ti,davinci-ctrl-ram-offset = <0>;
ti,davinci-ctrl-ram-size = <0x2000>;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <33
34
35
36
>;
};
};
nand_cs3@62000000 {
compatible = "ti,davinci-nand";
......
arch/arm/boot/dts/imx25.dtsi
View file @ b4b50fd7
......@@ -13,19 +13,35 @@
/ {
aliases {
gpio0 = &gpio1;
gpio1 = &gpio2;
gpio2 = &gpio3;
gpio3 = &gpio4;
i2c0 = &i2c1;
i2c1 = &i2c2;
i2c2 = &i2c3;
serial0 = &uart1;
serial1 = &uart2;
serial2 = &uart3;
serial3 = &uart4;
serial4 = &uart5;
gpio0 = &gpio1;
gpio1 = &gpio2;
gpio2 = &gpio3;
gpio3 = &gpio4;
spi0 = &spi1;
spi1 = &spi2;
spi2 = &spi3;
usb0 = &usbotg;
usb1 = &usbhost1;
};
cpus {
#address-cells = <0>;
#size-cells = <0>;
cpu {
compatible = "arm,arm926ej-s";
device_type = "cpu";
};
};
asic: asic-interrupt-controller@68000000 {
compatible = "fsl,imx25-asic", "fsl,avic";
interrupt-controller;
......@@ -377,7 +393,8 @@ esdhc2: esdhc@53fb8000 {
status = "disabled";
};
lcdc@53fbc000 {
lcdc: lcdc@53fbc000 {
compatible = "fsl,imx25-fb", "fsl,imx21-fb";
reg = <0x53fbc000 0x4000>;
interrupts = <39>;
clocks = <&clks 103>, <&clks 66>, <&clks 49>;
......@@ -424,6 +441,7 @@ sdma@53fd4000 {
reg = <0x53fd4000 0x4000>;
clocks = <&clks 112>, <&clks 68>;
clock-names = "ipg", "ahb";
#dma-cells = <3>;
interrupts = <34>;
};
......@@ -444,6 +462,13 @@ pwm1: pwm@53fe0000 {
interrupts = <26>;
};
iim: iim@53ff0000 {
compatible = "fsl,imx25-iim", "fsl,imx27-iim";
reg = <0x53ff0000 0x4000>;
interrupts = <19>;
clocks = <&clks 99>;
};
usbphy1: usbphy@1 {
compatible = "nop-usbphy";
status = "disabled";
......
arch/arm/boot/dts/imx27-apf27dev.dts
View file @ b4b50fd7
......@@ -53,6 +53,11 @@ &cspi2 {
&i2c1 {
clock-frequency = <400000>;
status = "okay";
rtc@68 {
compatible = "dallas,ds1374";
reg = <0x68>;
};
};
&i2c2 {
......
arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts 0 → 100644
View file @ b4b50fd7
/*
* Copyright 2012 Markus Pargmann, Pengutronix
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#include "imx27-phytec-phycard-s-som.dts"
/ {
model = "Phytec pca100 rapid development kit";
compatible = "phytec,imx27-pca100-rdk", "phytec,imx27-pca100", "fsl,imx27";
display: display {
model = "Primeview-PD050VL1";
native-mode = <&timing0>;
bits-per-pixel = <16>; /* non-standard but required */
fsl,pcr = <0xf0c88080>; /* non-standard but required */
display-timings {
timing0: 640x480 {
hactive = <640>;
vactive = <480>;
hback-porch = <112>;
hfront-porch = <36>;
hsync-len = <32>;
vback-porch = <33>;
vfront-porch = <33>;
vsync-len = <2>;
clock-frequency = <25000000>;
};
};
};
regulators {
compatible = "simple-bus";
reg_3v3: 3v3 {
compatible = "regulator-fixed";
regulator-name = "3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
};
};
&fb {
display = <&display>;
status = "okay";
};
&i2c1 {
status = "okay";
rtc@51 {
compatible = "nxp,pcf8563";
reg = <0x51>;
};
adc@64 {
compatible = "maxim,max1037";
vcc-supply = <&reg_3v3>;
reg = <0x64>;
};
};
&owire {
status = "okay";
};
&sdhci2 {
cd-gpios = <&gpio3 29 0>;
status = "okay";
};
&uart1 {
fsl,uart-has-rtscts;
status = "okay";
};
&uart2 {
fsl,uart-has-rtscts;
status = "okay";
};
&uart3 {
fsl,uart-has-rtscts;
status = "okay";
};
arch/arm/boot/dts/imx27-phytec-phycard-s-som.dts 0 → 100644
View file @ b4b50fd7
/*
* Copyright 2012 Sascha Hauer, Uwe Kleine-König, Steffen Trumtrar
* and Markus Pargmann, Pengutronix
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/dts-v1/;
#include "imx27.dtsi"
/ {
model = "Phytec pca100";
compatible = "phytec,imx27-pca100", "fsl,imx27";
memory {
reg = <0xa0000000 0x08000000>; /* 128MB */
};
};
&cspi1 {
fsl,spi-num-chipselects = <2>;
cs-gpios = <&gpio4 28 0>,
<&gpio4 27 0>;
status = "okay";
};
&fec {
status = "okay";
};
&i2c2 {
status = "okay";
at24@52 {
compatible = "at,24c32";
pagesize = <32>;
reg = <0x52>;
};
};
arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts
View file @ b4b50fd7
......@@ -35,3 +35,16 @@ &uart2 {
fsl,uart-has-rtscts;
status = "okay";
};
&weim {
can@d4000000 {
compatible = "nxp,sja1000";
reg = <4 0x00000000 0x00000100>;
interrupt-parent = <&gpio5>;
interrupts = <19 0x2>;
nxp,external-clock-frequency = <16000000>;
nxp,tx-output-config = <0x16>;
nxp,no-comparator-bypass;
fsl,weim-cs-timing = <0x0000dcf6 0x444a0301 0x44443302>;
};
};
arch/arm/boot/dts/imx27-phytec-phycore-som.dts
View file @ b4b50fd7
......@@ -17,49 +17,22 @@ / {
compatible = "phytec,imx27-pcm038", "fsl,imx27";
memory {
reg = <0x0 0x0>;
reg = <0xa0000000 0x08000000>;
};
};
soc {
aipi@10000000 { /* aipi1 */
serial@1000a000 {
status = "okay";
};
i2c@1001d000 {
clock-frequency = <400000>;
status = "okay";
at24@52 {
compatible = "at,24c32";
pagesize = <32>;
reg = <0x52>;
};
pcf8563@51 {
compatible = "nxp,pcf8563";
reg = <0x51>;
};
lm75@4a {
compatible = "national,lm75";
reg = <0x4a>;
};
};
};
&audmux {
status = "okay";
aipi@10020000 { /* aipi2 */
ethernet@1002b000 {
phy-reset-gpios = <&gpio3 30 0>;
status = "okay";
};
};
/* SSI0 <=> PINS_4 (MC13783 Audio) */
ssi0 {
fsl,audmux-port = <0>;
fsl,port-config = <0xcb205000>;
};
nor_flash@c0000000 {
compatible = "cfi-flash";
bank-width = <2>;
reg = <0xc0000000 0x02000000>;
linux,mtd-name = "physmap-flash.0";
#address-cells = <1>;
#size-cells = <1>;
pins4 {
fsl,audmux-port = <2>;
fsl,port-config = <0x00001000>;
};
};
......@@ -80,28 +53,16 @@ pmic: mc13783@0 {
fsl,mc13xxx-uses-rtc;
regulators {
sw1a_reg: sw1a {
/* SW1A and SW1B joined operation */
sw1_reg: sw1a {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-max-microvolt = <1520000>;
regulator-always-on;
regulator-boot-on;
};
sw1b_reg: sw1b {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
regulator-boot-on;
};
sw2a_reg: sw2a {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
sw2b_reg: sw2b {
/* SW2A and SW2B joined operation */
sw2_reg: sw2a {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
......@@ -172,8 +133,62 @@ pwgt1spi_reg: pwgt1spi {
};
};
&fec {
phy-reset-gpios = <&gpio3 30 0>;
status = "okay";
};
&i2c2 {
clock-frequency = <400000>;
status = "okay";
at24@52 {
compatible = "at,24c32";
pagesize = <32>;
reg = <0x52>;
};
pcf8563@51 {
compatible = "nxp,pcf8563";
reg = <0x51>;
};
lm75@4a {
compatible = "national,lm75";
reg = <0x4a>;
};
};
&nfc {
nand-bus-width = <8>;
nand-ecc-mode = "hw";
status = "okay";
};
&uart1 {
status = "okay";
};
&weim {
status = "okay";
nor: nor@c0000000 {
compatible = "cfi-flash";
reg = <0 0x00000000 0x02000000>;
bank-width = <2>;
linux,mtd-name = "physmap-flash.0";
fsl,weim-cs-timing = <0x22c2cf00 0x75000d01 0x00000900>;
#address-cells = <1>;
#size-cells = <1>;
};
sram: sram@c8000000 {
compatible = "mtd-ram";
reg = <1 0x00000000 0x00800000>;
bank-width = <2>;
linux,mtd-name = "mtd-ram.0";
fsl,weim-cs-timing = <0x0000d843 0x22252521 0x22220a00>;
#address-cells = <1>;
#size-cells = <1>;
};
};
arch/arm/boot/dts/imx27.dtsi
View file @ b4b50fd7
......@@ -13,25 +13,27 @@
/ {
aliases {
serial0 = &uart1;
serial1 = &uart2;
serial2 = &uart3;
serial3 = &uart4;
serial4 = &uart5;
serial5 = &uart6;
gpio0 = &gpio1;
gpio1 = &gpio2;
gpio2 = &gpio3;
gpio3 = &gpio4;
gpio4 = &gpio5;
gpio5 = &gpio6;
i2c0 = &i2c1;
i2c1 = &i2c2;
serial0 = &uart1;
serial1 = &uart2;
serial2 = &uart3;
serial3 = &uart4;
serial4 = &uart5;
serial5 = &uart6;
spi0 = &cspi1;
spi1 = &cspi2;
spi2 = &cspi3;
};
avic: avic-interrupt-controller@e0000000 {
compatible = "fsl,imx27-avic", "fsl,avic";
aitc: aitc-interrupt-controller@e0000000 {
compatible = "fsl,imx27-aitc", "fsl,avic";
interrupt-controller;
#interrupt-cells = <1>;
reg = <0x10040000 0x1000>;
......@@ -47,11 +49,29 @@ osc26m {
};
};
cpus {
#size-cells = <0>;
#address-cells = <1>;
cpu: cpu@0 {
device_type = "cpu";
compatible = "arm,arm926ej-s";
operating-points = <
/* kHz uV */
266000 1300000
399000 1450000
>;
clock-latency = <62500>;
clocks = <&clks 18>;
voltage-tolerance = <5>;
};
};
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
interrupt-parent = <&avic>;
interrupt-parent = <&aitc>;
ranges;
aipi@10000000 { /* AIPI1 */
......@@ -75,7 +95,7 @@ wdog: wdog@10002000 {
compatible = "fsl,imx27-wdt", "fsl,imx21-wdt";
reg = <0x10002000 0x1000>;
interrupts = <27>;
clocks = <&clks 0>;
clocks = <&clks 74>;
};
gpt1: timer@10003000 {
......@@ -102,7 +122,7 @@ gpt3: timer@10005000 {
clock-names = "ipg", "per";
};
pwm0: pwm@10006000 {
pwm: pwm@10006000 {
compatible = "fsl,imx27-pwm";
reg = <0x10006000 0x1000>;
interrupts = <23>;
......@@ -110,6 +130,21 @@ pwm0: pwm@10006000 {
clock-names = "ipg", "per";
};
kpp: kpp@10008000 {
compatible = "fsl,imx27-kpp", "fsl,imx21-kpp";
reg = <0x10008000 0x1000>;
interrupts = <21>;
clocks = <&clks 37>;
status = "disabled";
};
owire: owire@10009000 {
compatible = "fsl,imx27-owire", "fsl,imx21-owire";
reg = <0x10009000 0x1000>;
clocks = <&clks 35>;
status = "disabled";
};
uart1: serial@1000a000 {
compatible = "fsl,imx27-uart", "fsl,imx21-uart";
reg = <0x1000a000 0x1000>;
......@@ -260,6 +295,14 @@ gpio6: gpio@10015500 {
#interrupt-cells = <2>;
};
audmux: audmux@10016000 {
compatible = "fsl,imx27-audmux", "fsl,imx21-audmux";
reg = <0x10016000 0x1000>;
clocks = <&clks 0>;
clock-names = "audmux";
status = "disabled";
};
cspi3: cspi@10017000 {
#address-cells = <1>;
#size-cells = <0>;
......@@ -342,6 +385,15 @@ aipi@10020000 { /* AIPI2 */
reg = <0x10020000 0x20000>;
ranges;
fb: fb@10021000 {
compatible = "fsl,imx27-fb", "fsl,imx21-fb";
interrupts = <61>;
reg = <0x10021000 0x1000>;
clocks = <&clks 36>, <&clks 65>, <&clks 59>;
clock-names = "ipg", "ahb", "per";
status = "disabled";
};
coda: coda@10023000 {
compatible = "fsl,imx27-vpu";
reg = <0x10023000 0x0200>;
......@@ -351,27 +403,37 @@ coda: coda@10023000 {
iram = <&iram>;
};
sahara2: sahara@10025000 {
compatible = "fsl,imx27-sahara";
reg = <0x10025000 0x1000>;
interrupts = <59>;
clocks = <&clks 32>, <&clks 64>;
clock-names = "ipg", "ahb";
};
clks: ccm@10027000{
compatible = "fsl,imx27-ccm";
reg = <0x10027000 0x1000>;
#clock-cells = <1>;
};
iim: iim@10028000 {
compatible = "fsl,imx27-iim";
reg = <0x10028000 0x1000>;
interrupts = <62>;
clocks = <&clks 38>;
};
fec: ethernet@1002b000 {
compatible = "fsl,imx27-fec";
reg = <0x1002b000 0x4000>;
interrupts = <50>;
clocks = <&clks 48>, <&clks 67>, <&clks 0>;
clock-names = "ipg", "ahb", "ptp";
clocks = <&clks 48>, <&clks 67>;
clock-names = "ipg", "ahb";
status = "disabled";
};
};
iram: iram@ffff4c00 {
compatible = "mmio-sram";
reg = <0xffff4c00 0xb400>;
};
nfc: nand@d8000000 {
#address-cells = <1>;
#size-cells = <1>;
......@@ -381,5 +443,27 @@ nfc: nand@d8000000 {
clocks = <&clks 54>;
status = "disabled";
};
weim: weim@d8002000 {
#address-cells = <2>;
#size-cells = <1>;
compatible = "fsl,imx27-weim";
reg = <0xd8002000 0x1000>;
clocks = <&clks 0>;
ranges = <
0 0 0xc0000000 0x08000000
1 0 0xc8000000 0x08000000
2 0 0xd0000000 0x02000000
3 0 0xd2000000 0x02000000
4 0 0xd4000000 0x02000000
5 0 0xd6000000 0x02000000
>;
status = "disabled";
};
iram: iram@ffff4c00 {
compatible = "mmio-sram";
reg = <0xffff4c00 0xb400>;
};
};
};
arch/arm/boot/dts/imx31.dtsi
View file @ b4b50fd7
......@@ -20,6 +20,16 @@ aliases {
serial4 = &uart5;
};
cpus {
#address-cells = <0>;
#size-cells = <0>;
cpu {
compatible = "arm,arm1136";
device_type = "cpu";
};
};
avic: avic-interrupt-controller@60000000 {
compatible = "fsl,imx31-avic", "fsl,avic";
interrupt-controller;
......@@ -94,6 +104,13 @@ uart3: serial@5000c000 {
status = "disabled";
};
iim: iim@5001c000 {
compatible = "fsl,imx31-iim", "fsl,imx27-iim";
reg = <0x5001c000 0x1000>;
interrupts = <19>;
clocks = <&clks 25>;
};
clks: ccm@53f80000{
compatible = "fsl,imx31-ccm";
reg = <0x53f80000 0x4000>;
......
arch/arm/boot/dts/imx51-apf51.dts
View file @ b4b50fd7
......@@ -26,10 +26,6 @@ memory {
};
clocks {
ckih1 {
clock-frequency = <0>;
};
osc {
clock-frequency = <33554432>;
};
......
arch/arm/boot/dts/imx51-babbage.dts
View file @ b4b50fd7
......@@ -63,6 +63,10 @@ sound {
};
clocks {
ckih1 {
clock-frequency = <22579200>;
};
clk_26M: codec_clock {
compatible = "fixed-clock";
reg=<0>;
......@@ -108,6 +112,7 @@ pmic: mc13892@0 {
#size-cells = <0>;
compatible = "fsl,mc13892";
spi-max-frequency = <6000000>;
spi-cs-high;
reg = <0>;
interrupt-parent = <&gpio1>;
interrupts = <8 0x4>;
......
arch/arm/boot/dts/imx51.dtsi
View file @ b4b50fd7
This diff is collapsed.
arch/arm/boot/dts/imx53-qsb.dts
View file @ b4b50fd7
......@@ -93,6 +93,15 @@ reg_3p2v: 3p2v {
regulator-max-microvolt = <3200000>;
regulator-always-on;
};
reg_usb_vbus: usb_vbus {
compatible = "regulator-fixed";
regulator-name = "usb_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio7 8 0>;
enable-active-high;
};
};
sound {
......@@ -145,6 +154,7 @@ MX53_PAD_EIM_DA11__GPIO3_11 0x80000000
MX53_PAD_EIM_DA12__GPIO3_12 0x80000000
MX53_PAD_EIM_DA13__GPIO3_13 0x80000000
MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000
MX53_PAD_PATA_DA_2__GPIO7_8 0x80000000
MX53_PAD_GPIO_16__GPIO7_11 0x80000000
>;
};
......@@ -297,8 +307,14 @@ &fec {
status = "okay";
};
&vpu {
status = "okay";
};
&usbh1 {
status = "okay";
vbus-supply = <&reg_usb_vbus>;
phy_type = "utmi";
status = "okay";
};
&usbotg {
......
arch/arm/boot/dts/imx53.dtsi
View file @ b4b50fd7
......@@ -15,11 +15,6 @@
/ {
aliases {
serial0 = &uart1;
serial1 = &uart2;
serial2 = &uart3;
serial3 = &uart4;
serial4 = &uart5;
gpio0 = &gpio1;
gpio1 = &gpio2;
gpio2 = &gpio3;
......@@ -30,6 +25,24 @@ aliases {
i2c0 = &i2c1;
i2c1 = &i2c2;
i2c2 = &i2c3;
serial0 = &uart1;
serial1 = &uart2;
serial2 = &uart3;
serial3 = &uart4;
serial4 = &uart5;
spi0 = &ecspi1;
spi1 = &ecspi2;
spi2 = &cspi;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a8";
reg = <0x0>;
};
};
tzic: tz-interrupt-controller@0fffc000 {
......@@ -140,6 +153,9 @@ ssi2: ssi@50014000 {
reg = <0x50014000 0x4000>;
interrupts = <30>;
clocks = <&clks 49>;
dmas = <&sdma 24 1 0>,
<&sdma 25 1 0>;
dma-names = "rx", "tx";
fsl,fifo-depth = <15>;
fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
status = "disabled";
......@@ -957,6 +973,13 @@ aips@60000000 { /* AIPS2 */
reg = <0x60000000 0x10000000>;
ranges;
iim: iim@63f98000 {
compatible = "fsl,imx53-iim", "fsl,imx27-iim";
reg = <0x63f98000 0x4000>;
interrupts = <69>;
clocks = <&clks 107>;
};
uart5: serial@63f90000 {
compatible = "fsl,imx53-uart", "fsl,imx21-uart";
reg = <0x63f90000 0x4000>;
......@@ -990,6 +1013,7 @@ sdma: sdma@63fb0000 {
interrupts = <6>;
clocks = <&clks 56>, <&clks 56>;
clock-names = "ipg", "ahb";
#dma-cells = <3>;
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
};
......@@ -1029,6 +1053,9 @@ ssi1: ssi@63fcc000 {
reg = <0x63fcc000 0x4000>;
interrupts = <29>;
clocks = <&clks 48>;
dmas = <&sdma 28 0 0>,
<&sdma 29 0 0>;
dma-names = "rx", "tx";
fsl,fifo-depth = <15>;
fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
status = "disabled";
......@@ -1053,6 +1080,9 @@ ssi3: ssi@63fe8000 {
reg = <0x63fe8000 0x4000>;
interrupts = <96>;
clocks = <&clks 50>;
dmas = <&sdma 46 0 0>,
<&sdma 47 0 0>;
dma-names = "rx", "tx";
fsl,fifo-depth = <15>;
fsl,ssi-dma-events = <47 46 45 44>; /* TX0 RX0 TX1 RX1 */
status = "disabled";
......@@ -1076,6 +1106,22 @@ tve: tve@63ff0000 {
crtcs = <&ipu 1>;
status = "disabled";
};
vpu: vpu@63ff4000 {
compatible = "fsl,imx53-vpu";
reg = <0x63ff4000 0x1000>;
interrupts = <9>;
clocks = <&clks 63>, <&clks 63>;
clock-names = "per", "ahb";
iram = <&ocram>;
status = "disabled";
};
};
ocram: sram@f8000000 {
compatible = "mmio-sram";
reg = <0xf8000000 0x20000>;
clocks = <&clks 186>;
};
};
};
arch/arm/boot/dts/imx6dl-pinfunc.h
View file @ b4b50fd7
This diff is collapsed.
arch/arm/boot/dts/imx6dl-sabreauto.dts
View file @ b4b50fd7
......@@ -15,25 +15,3 @@ / {
model = "Freescale i.MX6 DualLite/Solo SABRE Automotive Board";
compatible = "fsl,imx6dl-sabreauto", "fsl,imx6dl";
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
hog {
pinctrl_hog: hoggrp {
fsl,pins = <
MX6DL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000
MX6DL_PAD_SD2_DAT2__GPIO1_IO13 0x80000000
>;
};
};
ecspi1 {
pinctrl_ecspi1_sabreauto: ecspi1-sabreauto {
fsl,pins = <
MX6DL_PAD_EIM_D19__GPIO3_IO19 0x80000000
>;
};
};
};
arch/arm/boot/dts/imx6dl-sabresd.dts
View file @ b4b50fd7
......@@ -15,22 +15,3 @@ / {
model = "Freescale i.MX6 DualLite SABRE Smart Device Board";
compatible = "fsl,imx6dl-sabresd", "fsl,imx6dl";
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
hog {
pinctrl_hog: hoggrp {
fsl,pins = <
MX6DL_PAD_GPIO_4__GPIO1_IO04 0x80000000
MX6DL_PAD_GPIO_5__GPIO1_IO05 0x80000000
MX6DL_PAD_NANDF_D0__GPIO2_IO00 0x80000000
MX6DL_PAD_NANDF_D1__GPIO2_IO01 0x80000000
MX6DL_PAD_NANDF_D2__GPIO2_IO02 0x80000000
MX6DL_PAD_NANDF_D3__GPIO2_IO03 0x80000000
MX6DL_PAD_GPIO_0__CCM_CLKO1 0x130b0
>;
};
};
};
arch/arm/boot/dts/imx6dl-wandboard.dts
View file @ b4b50fd7
......@@ -10,6 +10,7 @@
*/
/dts-v1/;
#include "imx6dl.dtsi"
#include "imx6qdl-wandboard.dtsi"
/ {
model = "Wandboard i.MX6 Dual Lite Board";
......@@ -19,26 +20,3 @@ memory {
reg = <0x10000000 0x40000000>;
};
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet_1>;
phy-mode = "rgmii";
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_1>;
status = "okay";
};
&usbh1 {
status = "okay";
};
&usdhc3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3_2>;
status = "okay";
};
arch/arm/boot/dts/imx6dl.dtsi
View file @ b4b50fd7
......@@ -8,8 +8,8 @@
*
*/
#include "imx6qdl.dtsi"
#include "imx6dl-pinfunc.h"
#include "imx6qdl.dtsi"
/ {
cpus {
......@@ -32,238 +32,15 @@ cpu@1 {
};
soc {
ocram: sram@00900000 {
compatible = "mmio-sram";
reg = <0x00900000 0x20000>;
clocks = <&clks 142>;
};
aips1: aips-bus@02000000 {
iomuxc: iomuxc@020e0000 {
compatible = "fsl,imx6dl-iomuxc";
reg = <0x020e0000 0x4000>;
audmux {
pinctrl_audmux_2: audmux-2 {
fsl,pins = <
MX6DL_PAD_CSI0_DAT7__AUD3_RXD 0x80000000
MX6DL_PAD_CSI0_DAT4__AUD3_TXC 0x80000000
MX6DL_PAD_CSI0_DAT5__AUD3_TXD 0x80000000
MX6DL_PAD_CSI0_DAT6__AUD3_TXFS 0x80000000
>;
};
};
ecspi1 {
pinctrl_ecspi1_1: ecspi1grp-1 {
fsl,pins = <
MX6DL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
MX6DL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
MX6DL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
>;
};
};
enet {
pinctrl_enet_1: enetgrp-1 {
fsl,pins = <
MX6DL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6DL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
MX6DL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
MX6DL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
MX6DL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
MX6DL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
MX6DL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
MX6DL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
MX6DL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
MX6DL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
MX6DL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
MX6DL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
MX6DL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
>;
};
pinctrl_enet_2: enetgrp-2 {
fsl,pins = <
MX6DL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0
MX6DL_PAD_KEY_COL2__ENET_MDC 0x1b0b0
MX6DL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
MX6DL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
MX6DL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
MX6DL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
MX6DL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
MX6DL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
MX6DL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
MX6DL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
MX6DL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
MX6DL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
>;
};
};
gpmi-nand {
pinctrl_gpmi_nand_1: gpmi-nand-1 {
fsl,pins = <
MX6DL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
MX6DL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
MX6DL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
MX6DL_PAD_NANDF_RB0__NAND_READY_B 0xb000
MX6DL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
MX6DL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
MX6DL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
MX6DL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
MX6DL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
MX6DL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
MX6DL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
MX6DL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
MX6DL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
MX6DL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
MX6DL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
MX6DL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
MX6DL_PAD_SD4_DAT0__NAND_DQS 0x00b1
>;
};
};
i2c1 {
pinctrl_i2c1_2: i2c1grp-2 {
fsl,pins = <
MX6DL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
MX6DL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
>;
};
};
uart1 {
pinctrl_uart1_1: uart1grp-1 {
fsl,pins = <
MX6DL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
MX6DL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
>;
};
};
uart4 {
pinctrl_uart4_1: uart4grp-1 {
fsl,pins = <
MX6DL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
MX6DL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
>;
};
};
usbotg {
pinctrl_usbotg_2: usbotggrp-2 {
fsl,pins = <
MX6DL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
>;
};
};
usdhc2 {
pinctrl_usdhc2_1: usdhc2grp-1 {
fsl,pins = <
MX6DL_PAD_SD2_CMD__SD2_CMD 0x17059
MX6DL_PAD_SD2_CLK__SD2_CLK 0x10059
MX6DL_PAD_SD2_DAT0__SD2_DATA0 0x17059
MX6DL_PAD_SD2_DAT1__SD2_DATA1 0x17059
MX6DL_PAD_SD2_DAT2__SD2_DATA2 0x17059
MX6DL_PAD_SD2_DAT3__SD2_DATA3 0x17059
MX6DL_PAD_NANDF_D4__SD2_DATA4 0x17059
MX6DL_PAD_NANDF_D5__SD2_DATA5 0x17059
MX6DL_PAD_NANDF_D6__SD2_DATA6 0x17059
MX6DL_PAD_NANDF_D7__SD2_DATA7 0x17059
>;
};
};
usdhc3 {
pinctrl_usdhc3_1: usdhc3grp-1 {
fsl,pins = <
MX6DL_PAD_SD3_CMD__SD3_CMD 0x17059
MX6DL_PAD_SD3_CLK__SD3_CLK 0x10059
MX6DL_PAD_SD3_DAT0__SD3_DATA0 0x17059
MX6DL_PAD_SD3_DAT1__SD3_DATA1 0x17059
MX6DL_PAD_SD3_DAT2__SD3_DATA2 0x17059
MX6DL_PAD_SD3_DAT3__SD3_DATA3 0x17059
MX6DL_PAD_SD3_DAT4__SD3_DATA4 0x17059
MX6DL_PAD_SD3_DAT5__SD3_DATA5 0x17059
MX6DL_PAD_SD3_DAT6__SD3_DATA6 0x17059
MX6DL_PAD_SD3_DAT7__SD3_DATA7 0x17059
>;
};
pinctrl_usdhc3_2: usdhc3grp_2 {
fsl,pins = <
MX6DL_PAD_SD3_CMD__SD3_CMD 0x17059
MX6DL_PAD_SD3_CLK__SD3_CLK 0x10059
MX6DL_PAD_SD3_DAT0__SD3_DATA0 0x17059
MX6DL_PAD_SD3_DAT1__SD3_DATA1 0x17059
MX6DL_PAD_SD3_DAT2__SD3_DATA2 0x17059
MX6DL_PAD_SD3_DAT3__SD3_DATA3 0x17059
>;
};
};
weim {
pinctrl_weim_cs0_1: weim_cs0grp-1 {
fsl,pins = <
MX6DL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1
>;
};
pinctrl_weim_nor_1: weim_norgrp-1 {
fsl,pins = <
MX6DL_PAD_EIM_OE__EIM_OE_B 0xb0b1
MX6DL_PAD_EIM_RW__EIM_RW 0xb0b1
MX6DL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060
/* data */
MX6DL_PAD_EIM_D16__EIM_DATA16 0x1b0b0
MX6DL_PAD_EIM_D17__EIM_DATA17 0x1b0b0
MX6DL_PAD_EIM_D18__EIM_DATA18 0x1b0b0
MX6DL_PAD_EIM_D19__EIM_DATA19 0x1b0b0
MX6DL_PAD_EIM_D20__EIM_DATA20 0x1b0b0
MX6DL_PAD_EIM_D21__EIM_DATA21 0x1b0b0
MX6DL_PAD_EIM_D22__EIM_DATA22 0x1b0b0
MX6DL_PAD_EIM_D23__EIM_DATA23 0x1b0b0
MX6DL_PAD_EIM_D24__EIM_DATA24 0x1b0b0
MX6DL_PAD_EIM_D25__EIM_DATA25 0x1b0b0
MX6DL_PAD_EIM_D26__EIM_DATA26 0x1b0b0
MX6DL_PAD_EIM_D27__EIM_DATA27 0x1b0b0
MX6DL_PAD_EIM_D28__EIM_DATA28 0x1b0b0
MX6DL_PAD_EIM_D29__EIM_DATA29 0x1b0b0
MX6DL_PAD_EIM_D30__EIM_DATA30 0x1b0b0
MX6DL_PAD_EIM_D31__EIM_DATA31 0x1b0b0
/* address */
MX6DL_PAD_EIM_A23__EIM_ADDR23 0xb0b1
MX6DL_PAD_EIM_A22__EIM_ADDR22 0xb0b1
MX6DL_PAD_EIM_A21__EIM_ADDR21 0xb0b1
MX6DL_PAD_EIM_A20__EIM_ADDR20 0xb0b1
MX6DL_PAD_EIM_A19__EIM_ADDR19 0xb0b1
MX6DL_PAD_EIM_A18__EIM_ADDR18 0xb0b1
MX6DL_PAD_EIM_A17__EIM_ADDR17 0xb0b1
MX6DL_PAD_EIM_A16__EIM_ADDR16 0xb0b1
MX6DL_PAD_EIM_DA15__EIM_AD15 0xb0b1
MX6DL_PAD_EIM_DA14__EIM_AD14 0xb0b1
MX6DL_PAD_EIM_DA13__EIM_AD13 0xb0b1
MX6DL_PAD_EIM_DA12__EIM_AD12 0xb0b1
MX6DL_PAD_EIM_DA11__EIM_AD11 0xb0b1
MX6DL_PAD_EIM_DA10__EIM_AD10 0xb0b1
MX6DL_PAD_EIM_DA9__EIM_AD09 0xb0b1
MX6DL_PAD_EIM_DA8__EIM_AD08 0xb0b1
MX6DL_PAD_EIM_DA7__EIM_AD07 0xb0b1
MX6DL_PAD_EIM_DA6__EIM_AD06 0xb0b1
MX6DL_PAD_EIM_DA5__EIM_AD05 0xb0b1
MX6DL_PAD_EIM_DA4__EIM_AD04 0xb0b1
MX6DL_PAD_EIM_DA3__EIM_AD03 0xb0b1
MX6DL_PAD_EIM_DA2__EIM_AD02 0xb0b1
MX6DL_PAD_EIM_DA1__EIM_AD01 0xb0b1
MX6DL_PAD_EIM_DA0__EIM_AD00 0xb0b1
>;
};
};
};
pxp: pxp@020f0000 {
......@@ -294,3 +71,20 @@ i2c4: i2c@021f8000 {
};
};
};
&ldb {
clocks = <&clks 33>, <&clks 34>,
<&clks 39>, <&clks 40>,
<&clks 135>, <&clks 136>;
clock-names = "di0_pll", "di1_pll",
"di0_sel", "di1_sel",
"di0", "di1";
lvds-channel@0 {
crtcs = <&ipu1 0>, <&ipu1 1>;
};
lvds-channel@1 {
crtcs = <&ipu1 0>, <&ipu1 1>;
};
};
arch/arm/boot/dts/imx6q-arm2.dts
View file @ b4b50fd7
This diff is collapsed.
arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi
View file @ b4b50fd7
This diff is collapsed.
arch/arm/boot/dts/imx6q-pinfunc.h
View file @ b4b50fd7
This diff is collapsed.
arch/arm/boot/dts/imx6q-sabreauto.dts
View file @ b4b50fd7
This diff is collapsed.
arch/arm/boot/dts/imx6q-sabrelite.dts
View file @ b4b50fd7
This diff is collapsed.
arch/arm/boot/dts/imx6q-sabresd.dts
View file @ b4b50fd7
This diff is collapsed.
arch/arm/boot/dts/imx6q-wandboard.dts 0 → 100644
View file @ b4b50fd7
This diff is collapsed.
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/dts-v1/;
/include/ "kirkwood.dtsi"
/include/ "kirkwood-6281.dtsi"
#include "kirkwood.dtsi"
#include "kirkwood-6281.dtsi"
/ {
model = "LaCie CloudBox";
......
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