Commit b623aae5 authored by Lucas De Marchi's avatar Lucas De Marchi

drm/i915/display: remove CNL ddi buf translation tables

The only real platform with DISPLAY_VER == 10 is GLK. We don't need to
handle CNL explicitly.
Signed-off-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210729162332.1774275-1-lucas.demarchi@intel.com
parent c27310e3
......@@ -1060,8 +1060,8 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
val = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN0(phy));
val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
RCOMP_SCALAR_MASK);
val |= SWING_SEL_UPPER(ddi_translations->entries[level].cnl.dw2_swing_sel);
val |= SWING_SEL_LOWER(ddi_translations->entries[level].cnl.dw2_swing_sel);
val |= SWING_SEL_UPPER(ddi_translations->entries[level].icl.dw2_swing_sel);
val |= SWING_SEL_LOWER(ddi_translations->entries[level].icl.dw2_swing_sel);
/* Program Rcomp scalar for every table entry */
val |= RCOMP_SCALAR(0x98);
intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), val);
......@@ -1072,16 +1072,16 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
val = intel_de_read(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy));
val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
CURSOR_COEFF_MASK);
val |= POST_CURSOR_1(ddi_translations->entries[level].cnl.dw4_post_cursor_1);
val |= POST_CURSOR_2(ddi_translations->entries[level].cnl.dw4_post_cursor_2);
val |= CURSOR_COEFF(ddi_translations->entries[level].cnl.dw4_cursor_coeff);
val |= POST_CURSOR_1(ddi_translations->entries[level].icl.dw4_post_cursor_1);
val |= POST_CURSOR_2(ddi_translations->entries[level].icl.dw4_post_cursor_2);
val |= CURSOR_COEFF(ddi_translations->entries[level].icl.dw4_cursor_coeff);
intel_de_write(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), val);
}
/* Program PORT_TX_DW7 */
val = intel_de_read(dev_priv, ICL_PORT_TX_DW7_LN0(phy));
val &= ~N_SCALAR_MASK;
val |= N_SCALAR(ddi_translations->entries[level].cnl.dw7_n_scalar);
val |= N_SCALAR(ddi_translations->entries[level].icl.dw7_n_scalar);
intel_de_write(dev_priv, ICL_PORT_TX_DW7_GRP(phy), val);
}
......
......@@ -25,7 +25,7 @@ struct bxt_ddi_buf_trans {
u8 deemphasis;
};
struct cnl_ddi_buf_trans {
struct icl_ddi_buf_trans {
u8 dw2_swing_sel;
u8 dw7_n_scalar;
u8 dw4_cursor_coeff;
......@@ -48,7 +48,7 @@ struct tgl_dkl_phy_ddi_buf_trans {
union intel_ddi_buf_trans_entry {
struct hsw_ddi_buf_trans hsw;
struct bxt_ddi_buf_trans bxt;
struct cnl_ddi_buf_trans cnl;
struct icl_ddi_buf_trans icl;
struct icl_mg_phy_ddi_buf_trans mg;
struct tgl_dkl_phy_ddi_buf_trans dkl;
};
......
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