Commit b7a3768b authored by Thomas Petazzoni's avatar Thomas Petazzoni Committed by Gregory CLEMENT

arm64: dts: marvell: add clocks for Armada AP806 XOR engines

The XORv2 engines in the AP side of the Armada 7K/8K SoCs are using the
AP MS core clock as input, so this commit adds the appropriate clocks
properties.
Signed-off-by: default avatarThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: default avatarGregory CLEMENT <gregory.clement@free-electrons.com>
parent 08332893
...@@ -159,6 +159,7 @@ xor@400000 { ...@@ -159,6 +159,7 @@ xor@400000 {
reg = <0x400000 0x1000>, reg = <0x400000 0x1000>,
<0x410000 0x1000>; <0x410000 0x1000>;
msi-parent = <&gic_v2m0>; msi-parent = <&gic_v2m0>;
clocks = <&ap_syscon 3>;
dma-coherent; dma-coherent;
}; };
...@@ -167,6 +168,7 @@ xor@420000 { ...@@ -167,6 +168,7 @@ xor@420000 {
reg = <0x420000 0x1000>, reg = <0x420000 0x1000>,
<0x430000 0x1000>; <0x430000 0x1000>;
msi-parent = <&gic_v2m0>; msi-parent = <&gic_v2m0>;
clocks = <&ap_syscon 3>;
dma-coherent; dma-coherent;
}; };
...@@ -175,6 +177,7 @@ xor@440000 { ...@@ -175,6 +177,7 @@ xor@440000 {
reg = <0x440000 0x1000>, reg = <0x440000 0x1000>,
<0x450000 0x1000>; <0x450000 0x1000>;
msi-parent = <&gic_v2m0>; msi-parent = <&gic_v2m0>;
clocks = <&ap_syscon 3>;
dma-coherent; dma-coherent;
}; };
...@@ -183,6 +186,7 @@ xor@460000 { ...@@ -183,6 +186,7 @@ xor@460000 {
reg = <0x460000 0x1000>, reg = <0x460000 0x1000>,
<0x470000 0x1000>; <0x470000 0x1000>;
msi-parent = <&gic_v2m0>; msi-parent = <&gic_v2m0>;
clocks = <&ap_syscon 3>;
dma-coherent; dma-coherent;
}; };
......
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