Commit b7ebf46e authored by Lorenzo Bianconi's avatar Lorenzo Bianconi Committed by Felix Fietkau

wifi: mt76: mt7915: enable wed for mt7986 chipset

Introduce wed tx support for MT7986 chipset
Tested-by: default avatarDaniel Golle <daniel@makrotopia.org>
Co-developed-by: default avatarBo Jiao <Bo.Jiao@mediatek.com>
Signed-off-by: default avatarBo Jiao <Bo.Jiao@mediatek.com>
Co-developed-by: default avatarSujuan Chen <sujuan.chen@mediatek.com>
Signed-off-by: default avatarSujuan Chen <sujuan.chen@mediatek.com>
Signed-off-by: default avatarLorenzo Bianconi <lorenzo@kernel.org>
Signed-off-by: default avatarFelix Fietkau <nbd@nbd.name>
parent 5498cee3
......@@ -324,6 +324,7 @@ static int mt7915_dma_enable(struct mt7915_dev *dev)
wed_irq_mask |= MT_INT_TX_DONE_BAND0 | MT_INT_TX_DONE_BAND1;
mt76_wr(dev, MT_INT_WED_MASK_CSR, wed_irq_mask);
mt76_wr(dev, MT_INT_MASK_CSR, wed_irq_mask);
mtk_wed_device_start(&dev->mt76.mmio.wed, wed_irq_mask);
}
......
......@@ -541,7 +541,18 @@ int mt7915_mmio_wed_init(struct mt7915_dev *dev, struct pci_dev *pdev,
wed->wlan.pci_dev = pdev;
wed->wlan.wpdma_phys = pci_resource_start(pdev, 0) +
MT_WFDMA_EXT_CSR_BASE;
wed->wlan.wpdma_int = pci_resource_start(pdev, 0) +
MT_INT_WED_SOURCE_CSR;
wed->wlan.wpdma_mask = pci_resource_start(pdev, 0) +
MT_INT_WED_MASK_CSR;
wed->wlan.wpdma_tx = pci_resource_start(pdev, 0) +
MT_TXQ_WED_RING_BASE;
wed->wlan.wpdma_txfree = pci_resource_start(pdev, 0) +
MT_RXQ_WED_RING_BASE;
wed->wlan.nbuf = 4096;
wed->wlan.tx_tbit[0] = MT_WED_TX_DONE_BAND0;
wed->wlan.tx_tbit[1] = MT_WED_TX_DONE_BAND1;
wed->wlan.txfree_tbit = MT_WED_TX_FREE_DONE;
wed->wlan.token_start = MT7915_TOKEN_SIZE - wed->wlan.nbuf;
wed->wlan.init_buf = mt7915_wed_init_buf;
wed->wlan.offload_enable = mt7915_mmio_wed_offload_enable;
......
......@@ -596,6 +596,7 @@ enum offs_rev {
#define MT_PCIE_RECOG_ID_MASK GENMASK(30, 0)
#define MT_PCIE_RECOG_ID_SEM BIT(31)
#define MT_INT_WED_SOURCE_CSR MT_WFDMA_EXT_CSR(0x200)
#define MT_INT_WED_MASK_CSR MT_WFDMA_EXT_CSR(0x204)
#define MT_WED_TX_RING_BASE MT_WFDMA_EXT_CSR(0x300)
......@@ -642,6 +643,13 @@ enum offs_rev {
#define MT_TXQ_EXT_CTRL(q) (MT_Q_BASE(__TXQ(q)) + 0x600 + \
MT_TXQ_ID(q)* 0x4)
#define MT_TXQ_WED_RING_BASE 0xd7300
#define MT_RXQ_WED_RING_BASE 0xd7410
#define MT_WED_TX_DONE_BAND0 4
#define MT_WED_TX_DONE_BAND1 5
#define MT_WED_TX_FREE_DONE 1
#define MT_INT_SOURCE_CSR __REG(INT_SOURCE_CSR)
#define MT_INT_MASK_CSR __REG(INT_MASK_CSR)
......
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