Commit b8618661 authored by Sascha Hauer's avatar Sascha Hauer

ARM: mx51: add imx-ssi devices

Signed-off-by: default avatarUwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: default avatarSascha Hauer <s.hauer@pengutronix.de>
parent 04b73b15
...@@ -949,6 +949,16 @@ DEFINE_CLOCK(fec_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG12_OFFSET, ...@@ -949,6 +949,16 @@ DEFINE_CLOCK(fec_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG12_OFFSET,
DEFINE_CLOCK1(nfc_clk, 0, MXC_CCM_CCGR5, MXC_CCM_CCGRx_CG10_OFFSET, DEFINE_CLOCK1(nfc_clk, 0, MXC_CCM_CCGR5, MXC_CCM_CCGRx_CG10_OFFSET,
clk_nfc, &emi_slow_clk, NULL); clk_nfc, &emi_slow_clk, NULL);
/* SSI */
DEFINE_CLOCK(ssi1_ipg_clk, 0, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG8_OFFSET,
NULL, NULL, &ipg_clk, NULL);
DEFINE_CLOCK(ssi1_clk, 0, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG9_OFFSET,
NULL, NULL, &pll3_sw_clk, &ssi1_ipg_clk);
DEFINE_CLOCK(ssi2_ipg_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG10_OFFSET,
NULL, NULL, &ipg_clk, NULL);
DEFINE_CLOCK(ssi2_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG11_OFFSET,
NULL, NULL, &pll3_sw_clk, &ssi2_ipg_clk);
/* eCSPI */ /* eCSPI */
DEFINE_CLOCK_FULL(ecspi1_ipg_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG9_OFFSET, DEFINE_CLOCK_FULL(ecspi1_ipg_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG9_OFFSET,
NULL, NULL, _clk_ccgr_enable_inrun, _clk_ccgr_disable, NULL, NULL, _clk_ccgr_enable_inrun, _clk_ccgr_disable,
...@@ -991,6 +1001,8 @@ static struct clk_lookup lookups[] = { ...@@ -991,6 +1001,8 @@ static struct clk_lookup lookups[] = {
_REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", ahb_clk) _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", ahb_clk)
_REGISTER_CLOCK("imx-keypad.0", NULL, kpp_clk) _REGISTER_CLOCK("imx-keypad.0", NULL, kpp_clk)
_REGISTER_CLOCK("mxc_nand", NULL, nfc_clk) _REGISTER_CLOCK("mxc_nand", NULL, nfc_clk)
_REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
_REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
_REGISTER_CLOCK("imx51-ecspi.0", NULL, ecspi1_clk) _REGISTER_CLOCK("imx51-ecspi.0", NULL, ecspi1_clk)
_REGISTER_CLOCK("imx51-ecspi.1", NULL, ecspi2_clk) _REGISTER_CLOCK("imx51-ecspi.1", NULL, ecspi2_clk)
_REGISTER_CLOCK("imx51-cspi.0", NULL, cspi_clk) _REGISTER_CLOCK("imx51-cspi.0", NULL, cspi_clk)
......
...@@ -13,6 +13,10 @@ extern const struct imx_imx_i2c_data imx51_imx_i2c_data[] __initconst; ...@@ -13,6 +13,10 @@ extern const struct imx_imx_i2c_data imx51_imx_i2c_data[] __initconst;
#define imx51_add_imx_i2c(id, pdata) \ #define imx51_add_imx_i2c(id, pdata) \
imx_add_imx_i2c(&imx51_imx_i2c_data[id], pdata) imx_add_imx_i2c(&imx51_imx_i2c_data[id], pdata)
extern const struct imx_imx_ssi_data imx51_imx_ssi_data[] __initconst;
#define imx51_add_imx_ssi(id, pdata) \
imx_add_imx_ssi(&imx51_imx_ssi_data[id], pdata)
extern const struct imx_imx_uart_1irq_data imx51_imx_uart_data[] __initconst; extern const struct imx_imx_uart_1irq_data imx51_imx_uart_data[] __initconst;
#define imx51_add_imx_uart(id, pdata) \ #define imx51_add_imx_uart(id, pdata) \
imx_add_imx_uart_1irq(&imx51_imx_uart_data[id], pdata) imx_add_imx_uart_1irq(&imx51_imx_uart_data[id], pdata)
......
...@@ -66,6 +66,15 @@ const struct imx_imx_ssi_data imx35_imx_ssi_data[] __initconst = { ...@@ -66,6 +66,15 @@ const struct imx_imx_ssi_data imx35_imx_ssi_data[] __initconst = {
}; };
#endif /* ifdef CONFIG_ARCH_MX35 */ #endif /* ifdef CONFIG_ARCH_MX35 */
#ifdef CONFIG_ARCH_MX51
const struct imx_imx_ssi_data imx51_imx_ssi_data[] __initconst = {
#define imx51_imx_ssi_data_entry(_id, _hwid) \
imx_imx_ssi_data_entry(MX51, _id, _hwid, SZ_4K)
imx51_imx_ssi_data_entry(0, 1),
imx51_imx_ssi_data_entry(1, 2),
};
#endif /* ifdef CONFIG_ARCH_MX51 */
struct platform_device *__init imx_add_imx_ssi( struct platform_device *__init imx_add_imx_ssi(
const struct imx_imx_ssi_data *data, const struct imx_imx_ssi_data *data,
const struct imx_ssi_platform_data *pdata) const struct imx_ssi_platform_data *pdata)
......
...@@ -248,14 +248,14 @@ ...@@ -248,14 +248,14 @@
#define MX51_DMA_REQ_UART1_TX 19 #define MX51_DMA_REQ_UART1_TX 19
#define MX51_DMA_REQ_SDHC1 20 #define MX51_DMA_REQ_SDHC1 20
#define MX51_DMA_REQ_SDHC2 21 #define MX51_DMA_REQ_SDHC2 21
#define MX51_DMA_REQ_SSI2_RX2 22 #define MX51_DMA_REQ_SSI2_RX1 22
#define MX51_DMA_REQ_SSI2_TX2 23 #define MX51_DMA_REQ_SSI2_TX1 23
#define MX51_DMA_REQ_SSI2_RX1 24 #define MX51_DMA_REQ_SSI2_RX0 24
#define MX51_DMA_REQ_SSI2_TX1 25 #define MX51_DMA_REQ_SSI2_TX0 25
#define MX51_DMA_REQ_SSI1_RX2 26 #define MX51_DMA_REQ_SSI1_RX1 26
#define MX51_DMA_REQ_SSI1_TX2 27 #define MX51_DMA_REQ_SSI1_TX1 27
#define MX51_DMA_REQ_SSI1_RX1 28 #define MX51_DMA_REQ_SSI1_RX0 28
#define MX51_DMA_REQ_SSI1_TX1 29 #define MX51_DMA_REQ_SSI1_TX0 29
#define MX51_DMA_REQ_EMI_RD 30 #define MX51_DMA_REQ_EMI_RD 30
#define MX51_DMA_REQ_CTI2_0 31 #define MX51_DMA_REQ_CTI2_0 31
#define MX51_DMA_REQ_EMI_WR 32 #define MX51_DMA_REQ_EMI_WR 32
...@@ -308,8 +308,8 @@ ...@@ -308,8 +308,8 @@
#define MX51_MXC_INT_RTIC 26 #define MX51_MXC_INT_RTIC 26
#define MX51_MXC_INT_CSU 27 #define MX51_MXC_INT_CSU 27
#define MX51_MXC_INT_SLIM_B 28 #define MX51_MXC_INT_SLIM_B 28
#define MX51_MXC_INT_SSI1 29 #define MX51_INT_SSI1 29
#define MX51_MXC_INT_SSI2 30 #define MX51_INT_SSI2 30
#define MX51_INT_UART1 31 #define MX51_INT_UART1 31
#define MX51_INT_UART2 32 #define MX51_INT_UART2 32
#define MX51_INT_UART3 33 #define MX51_INT_UART3 33
......
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