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Commit b8842451 authored by Grant Likely's avatar Grant Likely
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powerpc/5200: Trim cruft from device trees 

Trim out obsolete/extraneous properties and tighten up some usage
conventions.  Changes include:
- removal of device_type properties
- removal of cell-index properties
- Addition of gpio-controller and #gpio-cells properties to gpio
  nodes
- Move common interrupt-parent property out of device nodes and
  into top level parent node.

This patch also include what looks to be just trivial editorial
whitespace/format changes, but there is real method in this
madness.  Editorial changes were made to keep the all the
mpc5200 board device trees as similar as possible so that diffs
between them only show the real differences between the boards.
The pcm030 device tree was most affected by this because many
of the comments had been changed from // to /* */ style and
some cell values where changed from decimal to hex format when
it was cloned from one of the other 5200 device trees.
Signed-off-by: default avatarGrant Likely <grant.likely@secretlab.ca>
Reviewed-by: default avatarWolfram Sang <w.sang@pengutronix.de>
parent 3b5ebf8e
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Showing with 106 additions and 314 deletions
arch/powerpc/boot/dts/cm5200.dts
View file @ b8842451
...@@ -17,6 +17,7 @@ / { ...@@ -17,6 +17,7 @@ / {
compatible = "schindler,cm5200"; compatible = "schindler,cm5200";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
interrupt-parent = <&mpc5200_pic>;
cpus { cpus {
#address-cells = <1>; #address-cells = <1>;
...@@ -66,7 +67,6 @@ timer@600 { // General Purpose Timer ...@@ -66,7 +67,6 @@ timer@600 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
reg = <0x600 0x10>; reg = <0x600 0x10>;
interrupts = <1 9 0>; interrupts = <1 9 0>;
interrupt-parent = <&mpc5200_pic>;
fsl,has-wdt; fsl,has-wdt;
}; };
...@@ -74,84 +74,76 @@ timer@610 { // General Purpose Timer ...@@ -74,84 +74,76 @@ timer@610 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
reg = <0x610 0x10>; reg = <0x610 0x10>;
interrupts = <1 10 0>; interrupts = <1 10 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
timer@620 { // General Purpose Timer timer@620 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
reg = <0x620 0x10>; reg = <0x620 0x10>;
interrupts = <1 11 0>; interrupts = <1 11 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
timer@630 { // General Purpose Timer timer@630 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
reg = <0x630 0x10>; reg = <0x630 0x10>;
interrupts = <1 12 0>; interrupts = <1 12 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
timer@640 { // General Purpose Timer timer@640 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
reg = <0x640 0x10>; reg = <0x640 0x10>;
interrupts = <1 13 0>; interrupts = <1 13 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
timer@650 { // General Purpose Timer timer@650 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
reg = <0x650 0x10>; reg = <0x650 0x10>;
interrupts = <1 14 0>; interrupts = <1 14 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
timer@660 { // General Purpose Timer timer@660 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
reg = <0x660 0x10>; reg = <0x660 0x10>;
interrupts = <1 15 0>; interrupts = <1 15 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
timer@670 { // General Purpose Timer timer@670 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
reg = <0x670 0x10>; reg = <0x670 0x10>;
interrupts = <1 16 0>; interrupts = <1 16 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
rtc@800 { // Real time clock rtc@800 { // Real time clock
compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc"; compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
reg = <0x800 0x100>; reg = <0x800 0x100>;
interrupts = <1 5 0 1 6 0>; interrupts = <1 5 0 1 6 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
gpio@b00 { gpio_simple: gpio@b00 {
compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio"; compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
reg = <0xb00 0x40>; reg = <0xb00 0x40>;
interrupts = <1 7 0>; interrupts = <1 7 0>;
interrupt-parent = <&mpc5200_pic>; gpio-controller;
#gpio-cells = <2>;
}; };
gpio@c00 { gpio_wkup: gpio@c00 {
compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup"; compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
reg = <0xc00 0x40>; reg = <0xc00 0x40>;
interrupts = <1 8 0 0 3 0>; interrupts = <1 8 0 0 3 0>;
interrupt-parent = <&mpc5200_pic>; gpio-controller;
#gpio-cells = <2>;
}; };
spi@f00 { spi@f00 {
compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi"; compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
reg = <0xf00 0x20>; reg = <0xf00 0x20>;
interrupts = <2 13 0 2 14 0>; interrupts = <2 13 0 2 14 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
usb@1000 { usb@1000 {
compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be"; compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
reg = <0x1000 0xff>; reg = <0x1000 0xff>;
interrupts = <2 6 0>; interrupts = <2 6 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
dma-controller@1200 { dma-controller@1200 {
...@@ -161,7 +153,6 @@ dma-controller@1200 { ...@@ -161,7 +153,6 @@ dma-controller@1200 {
3 4 0 3 5 0 3 6 0 3 7 0 3 4 0 3 5 0 3 6 0 3 7 0
3 8 0 3 9 0 3 10 0 3 11 0 3 8 0 3 9 0 3 10 0 3 11 0
3 12 0 3 13 0 3 14 0 3 15 0>; 3 12 0 3 13 0 3 14 0 3 15 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
xlb@1f00 { xlb@1f00 {
...@@ -170,48 +161,34 @@ xlb@1f00 { ...@@ -170,48 +161,34 @@ xlb@1f00 {
}; };
serial@2000 { // PSC1 serial@2000 { // PSC1
device_type = "serial";
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
port-number = <0>; // Logical port assignment
reg = <0x2000 0x100>; reg = <0x2000 0x100>;
interrupts = <2 1 0>; interrupts = <2 1 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
serial@2200 { // PSC2 serial@2200 { // PSC2
device_type = "serial"; compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
compatible = "fsl,mpc5200-psc-uart";
port-number = <1>; // Logical port assignment
reg = <0x2200 0x100>; reg = <0x2200 0x100>;
interrupts = <2 2 0>; interrupts = <2 2 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
serial@2400 { // PSC3 serial@2400 { // PSC3
device_type = "serial"; compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
compatible = "fsl,mpc5200-psc-uart";
port-number = <2>; // Logical port assignment
reg = <0x2400 0x100>; reg = <0x2400 0x100>;
interrupts = <2 3 0>; interrupts = <2 3 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
serial@2c00 { // PSC6 serial@2c00 { // PSC6
device_type = "serial";
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
port-number = <5>; // Logical port assignment
reg = <0x2c00 0x100>; reg = <0x2c00 0x100>;
interrupts = <2 4 0>; interrupts = <2 4 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
ethernet@3000 { ethernet@3000 {
device_type = "network";
compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec"; compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
reg = <0x3000 0x400>; reg = <0x3000 0x400>;
local-mac-address = [ 00 00 00 00 00 00 ]; local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <2 5 0>; interrupts = <2 5 0>;
interrupt-parent = <&mpc5200_pic>;
phy-handle = <&phy0>; phy-handle = <&phy0>;
}; };
...@@ -221,10 +198,8 @@ mdio@3000 { ...@@ -221,10 +198,8 @@ mdio@3000 {
compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio"; compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co. interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
interrupt-parent = <&mpc5200_pic>;
phy0: ethernet-phy@0 { phy0: ethernet-phy@0 {
device_type = "ethernet-phy";
reg = <0>; reg = <0>;
}; };
}; };
...@@ -235,7 +210,6 @@ i2c@3d40 { ...@@ -235,7 +210,6 @@ i2c@3d40 {
compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
reg = <0x3d40 0x40>; reg = <0x3d40 0x40>;
interrupts = <2 16 0>; interrupts = <2 16 0>;
interrupt-parent = <&mpc5200_pic>;
fsl5200-clocking; fsl5200-clocking;
}; };
...@@ -245,9 +219,8 @@ sram@8000 { ...@@ -245,9 +219,8 @@ sram@8000 {
}; };
}; };
lpb { localbus {
model = "fsl,lpb"; compatible = "fsl,mpc5200b-lpb","simple-bus";
compatible = "fsl,lpb";
#address-cells = <2>; #address-cells = <2>;
#size-cells = <1>; #size-cells = <1>;
ranges = <0 0 0xfc000000 0x2000000>; ranges = <0 0 0xfc000000 0x2000000>;
......
arch/powerpc/boot/dts/lite5200.dts
View file @ b8842451
...@@ -17,6 +17,7 @@ / { ...@@ -17,6 +17,7 @@ / {
compatible = "fsl,lite5200"; compatible = "fsl,lite5200";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
interrupt-parent = <&mpc5200_pic>;
cpus { cpus {
#address-cells = <1>; #address-cells = <1>;
...@@ -58,96 +59,74 @@ mpc5200_pic: interrupt-controller@500 { ...@@ -58,96 +59,74 @@ mpc5200_pic: interrupt-controller@500 {
// 5200 interrupts are encoded into two levels; // 5200 interrupts are encoded into two levels;
interrupt-controller; interrupt-controller;
#interrupt-cells = <3>; #interrupt-cells = <3>;
device_type = "interrupt-controller";
compatible = "fsl,mpc5200-pic"; compatible = "fsl,mpc5200-pic";
reg = <0x500 0x80>; reg = <0x500 0x80>;
}; };
timer@600 { // General Purpose Timer timer@600 { // General Purpose Timer
compatible = "fsl,mpc5200-gpt"; compatible = "fsl,mpc5200-gpt";
cell-index = <0>;
reg = <0x600 0x10>; reg = <0x600 0x10>;
interrupts = <1 9 0>; interrupts = <1 9 0>;
interrupt-parent = <&mpc5200_pic>;
fsl,has-wdt; fsl,has-wdt;
}; };
timer@610 { // General Purpose Timer timer@610 { // General Purpose Timer
compatible = "fsl,mpc5200-gpt"; compatible = "fsl,mpc5200-gpt";
cell-index = <1>;
reg = <0x610 0x10>; reg = <0x610 0x10>;
interrupts = <1 10 0>; interrupts = <1 10 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
timer@620 { // General Purpose Timer timer@620 { // General Purpose Timer
compatible = "fsl,mpc5200-gpt"; compatible = "fsl,mpc5200-gpt";
cell-index = <2>;
reg = <0x620 0x10>; reg = <0x620 0x10>;
interrupts = <1 11 0>; interrupts = <1 11 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
timer@630 { // General Purpose Timer timer@630 { // General Purpose Timer
compatible = "fsl,mpc5200-gpt"; compatible = "fsl,mpc5200-gpt";
cell-index = <3>;
reg = <0x630 0x10>; reg = <0x630 0x10>;
interrupts = <1 12 0>; interrupts = <1 12 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
timer@640 { // General Purpose Timer timer@640 { // General Purpose Timer
compatible = "fsl,mpc5200-gpt"; compatible = "fsl,mpc5200-gpt";
cell-index = <4>;
reg = <0x640 0x10>; reg = <0x640 0x10>;
interrupts = <1 13 0>; interrupts = <1 13 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
timer@650 { // General Purpose Timer timer@650 { // General Purpose Timer
compatible = "fsl,mpc5200-gpt"; compatible = "fsl,mpc5200-gpt";
cell-index = <5>;
reg = <0x650 0x10>; reg = <0x650 0x10>;
interrupts = <1 14 0>; interrupts = <1 14 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
timer@660 { // General Purpose Timer timer@660 { // General Purpose Timer
compatible = "fsl,mpc5200-gpt"; compatible = "fsl,mpc5200-gpt";
cell-index = <6>;
reg = <0x660 0x10>; reg = <0x660 0x10>;
interrupts = <1 15 0>; interrupts = <1 15 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
timer@670 { // General Purpose Timer timer@670 { // General Purpose Timer
compatible = "fsl,mpc5200-gpt"; compatible = "fsl,mpc5200-gpt";
cell-index = <7>;
reg = <0x670 0x10>; reg = <0x670 0x10>;
interrupts = <1 16 0>; interrupts = <1 16 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
rtc@800 { // Real time clock rtc@800 { // Real time clock
compatible = "fsl,mpc5200-rtc"; compatible = "fsl,mpc5200-rtc";
reg = <0x800 0x100>; reg = <0x800 0x100>;
interrupts = <1 5 0 1 6 0>; interrupts = <1 5 0 1 6 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
can@900 { can@900 {
compatible = "fsl,mpc5200-mscan"; compatible = "fsl,mpc5200-mscan";
cell-index = <0>;
interrupts = <2 17 0>; interrupts = <2 17 0>;
interrupt-parent = <&mpc5200_pic>;
reg = <0x900 0x80>; reg = <0x900 0x80>;
}; };
can@980 { can@980 {
compatible = "fsl,mpc5200-mscan"; compatible = "fsl,mpc5200-mscan";
cell-index = <1>;
interrupts = <2 18 0>; interrupts = <2 18 0>;
interrupt-parent = <&mpc5200_pic>;
reg = <0x980 0x80>; reg = <0x980 0x80>;
}; };
...@@ -155,39 +134,33 @@ gpio@b00 { ...@@ -155,39 +134,33 @@ gpio@b00 {
compatible = "fsl,mpc5200-gpio"; compatible = "fsl,mpc5200-gpio";
reg = <0xb00 0x40>; reg = <0xb00 0x40>;
interrupts = <1 7 0>; interrupts = <1 7 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
gpio@c00 { gpio@c00 {
compatible = "fsl,mpc5200-gpio-wkup"; compatible = "fsl,mpc5200-gpio-wkup";
reg = <0xc00 0x40>; reg = <0xc00 0x40>;
interrupts = <1 8 0 0 3 0>; interrupts = <1 8 0 0 3 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
spi@f00 { spi@f00 {
compatible = "fsl,mpc5200-spi"; compatible = "fsl,mpc5200-spi";
reg = <0xf00 0x20>; reg = <0xf00 0x20>;
interrupts = <2 13 0 2 14 0>; interrupts = <2 13 0 2 14 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
usb@1000 { usb@1000 {
compatible = "fsl,mpc5200-ohci","ohci-be"; compatible = "fsl,mpc5200-ohci","ohci-be";
reg = <0x1000 0xff>; reg = <0x1000 0xff>;
interrupts = <2 6 0>; interrupts = <2 6 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
dma-controller@1200 { dma-controller@1200 {
device_type = "dma-controller";
compatible = "fsl,mpc5200-bestcomm"; compatible = "fsl,mpc5200-bestcomm";
reg = <0x1200 0x80>; reg = <0x1200 0x80>;
interrupts = <3 0 0 3 1 0 3 2 0 3 3 0 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
3 4 0 3 5 0 3 6 0 3 7 0 3 4 0 3 5 0 3 6 0 3 7 0
3 8 0 3 9 0 3 10 0 3 11 0 3 8 0 3 9 0 3 10 0 3 11 0
3 12 0 3 13 0 3 14 0 3 15 0>; 3 12 0 3 13 0 3 14 0 3 15 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
xlb@1f00 { xlb@1f00 {
...@@ -196,13 +169,10 @@ xlb@1f00 { ...@@ -196,13 +169,10 @@ xlb@1f00 {
}; };
serial@2000 { // PSC1 serial@2000 { // PSC1
device_type = "serial";
compatible = "fsl,mpc5200-psc-uart"; compatible = "fsl,mpc5200-psc-uart";
port-number = <0>; // Logical port assignment
cell-index = <0>; cell-index = <0>;
reg = <0x2000 0x100>; reg = <0x2000 0x100>;
interrupts = <2 1 0>; interrupts = <2 1 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
// PSC2 in ac97 mode example // PSC2 in ac97 mode example
...@@ -211,7 +181,6 @@ serial@2000 { // PSC1 ...@@ -211,7 +181,6 @@ serial@2000 { // PSC1
// cell-index = <1>; // cell-index = <1>;
// reg = <0x2200 0x100>; // reg = <0x2200 0x100>;
// interrupts = <2 2 0>; // interrupts = <2 2 0>;
// interrupt-parent = <&mpc5200_pic>;
//}; //};
// PSC3 in CODEC mode example // PSC3 in CODEC mode example
...@@ -220,27 +189,22 @@ serial@2000 { // PSC1 ...@@ -220,27 +189,22 @@ serial@2000 { // PSC1
// cell-index = <2>; // cell-index = <2>;
// reg = <0x2400 0x100>; // reg = <0x2400 0x100>;
// interrupts = <2 3 0>; // interrupts = <2 3 0>;
// interrupt-parent = <&mpc5200_pic>;
//}; //};
// PSC4 in uart mode example // PSC4 in uart mode example
//serial@2600 { // PSC4 //serial@2600 { // PSC4
// device_type = "serial";
// compatible = "fsl,mpc5200-psc-uart"; // compatible = "fsl,mpc5200-psc-uart";
// cell-index = <3>; // cell-index = <3>;
// reg = <0x2600 0x100>; // reg = <0x2600 0x100>;
// interrupts = <2 11 0>; // interrupts = <2 11 0>;
// interrupt-parent = <&mpc5200_pic>;
//}; //};
// PSC5 in uart mode example // PSC5 in uart mode example
//serial@2800 { // PSC5 //serial@2800 { // PSC5
// device_type = "serial";
// compatible = "fsl,mpc5200-psc-uart"; // compatible = "fsl,mpc5200-psc-uart";
// cell-index = <4>; // cell-index = <4>;
// reg = <0x2800 0x100>; // reg = <0x2800 0x100>;
// interrupts = <2 12 0>; // interrupts = <2 12 0>;
// interrupt-parent = <&mpc5200_pic>;
//}; //};
// PSC6 in spi mode example // PSC6 in spi mode example
...@@ -249,16 +213,13 @@ serial@2000 { // PSC1 ...@@ -249,16 +213,13 @@ serial@2000 { // PSC1
// cell-index = <5>; // cell-index = <5>;
// reg = <0x2c00 0x100>; // reg = <0x2c00 0x100>;
// interrupts = <2 4 0>; // interrupts = <2 4 0>;
// interrupt-parent = <&mpc5200_pic>;
//}; //};
ethernet@3000 { ethernet@3000 {
device_type = "network";
compatible = "fsl,mpc5200-fec"; compatible = "fsl,mpc5200-fec";
reg = <0x3000 0x400>; reg = <0x3000 0x400>;
local-mac-address = [ 00 00 00 00 00 00 ]; local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <2 5 0>; interrupts = <2 5 0>;
interrupt-parent = <&mpc5200_pic>;
phy-handle = <&phy0>; phy-handle = <&phy0>;
}; };
...@@ -268,30 +229,24 @@ mdio@3000 { ...@@ -268,30 +229,24 @@ mdio@3000 {
compatible = "fsl,mpc5200-mdio"; compatible = "fsl,mpc5200-mdio";
reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co. interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
interrupt-parent = <&mpc5200_pic>;
phy0: ethernet-phy@1 { phy0: ethernet-phy@1 {
device_type = "ethernet-phy";
reg = <1>; reg = <1>;
}; };
}; };
ata@3a00 { ata@3a00 {
device_type = "ata";
compatible = "fsl,mpc5200-ata"; compatible = "fsl,mpc5200-ata";
reg = <0x3a00 0x100>; reg = <0x3a00 0x100>;
interrupts = <2 7 0>; interrupts = <2 7 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
i2c@3d00 { i2c@3d00 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
compatible = "fsl,mpc5200-i2c","fsl-i2c"; compatible = "fsl,mpc5200-i2c","fsl-i2c";
cell-index = <0>;
reg = <0x3d00 0x40>; reg = <0x3d00 0x40>;
interrupts = <2 15 0>; interrupts = <2 15 0>;
interrupt-parent = <&mpc5200_pic>;
fsl5200-clocking; fsl5200-clocking;
}; };
...@@ -299,14 +254,12 @@ i2c@3d40 { ...@@ -299,14 +254,12 @@ i2c@3d40 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
compatible = "fsl,mpc5200-i2c","fsl-i2c"; compatible = "fsl,mpc5200-i2c","fsl-i2c";
cell-index = <1>;
reg = <0x3d40 0x40>; reg = <0x3d40 0x40>;
interrupts = <2 16 0>; interrupts = <2 16 0>;
interrupt-parent = <&mpc5200_pic>;
fsl5200-clocking; fsl5200-clocking;
}; };
sram@8000 { sram@8000 {
compatible = "fsl,mpc5200-sram","sram"; compatible = "fsl,mpc5200-sram";
reg = <0x8000 0x4000>; reg = <0x8000 0x4000>;
}; };
}; };
...@@ -325,7 +278,6 @@ pci@f0000d00 { ...@@ -325,7 +278,6 @@ pci@f0000d00 {
0xc000 0 0 4 &mpc5200_pic 0 0 3>; 0xc000 0 0 4 &mpc5200_pic 0 0 3>;
clock-frequency = <0>; // From boot loader clock-frequency = <0>; // From boot loader
interrupts = <2 8 0 2 9 0 2 10 0>; interrupts = <2 8 0 2 9 0 2 10 0>;
interrupt-parent = <&mpc5200_pic>;
bus-range = <0 0>; bus-range = <0 0>;
ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000 ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000
0x02000000 0 0xa0000000 0xa0000000 0 0x10000000 0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
......
arch/powerpc/boot/dts/lite5200b.dts
View file @ b8842451
...@@ -17,6 +17,7 @@ / { ...@@ -17,6 +17,7 @@ / {
compatible = "fsl,lite5200b"; compatible = "fsl,lite5200b";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
interrupt-parent = <&mpc5200_pic>;
cpus { cpus {
#address-cells = <1>; #address-cells = <1>;
...@@ -58,136 +59,112 @@ mpc5200_pic: interrupt-controller@500 { ...@@ -58,136 +59,112 @@ mpc5200_pic: interrupt-controller@500 {
// 5200 interrupts are encoded into two levels; // 5200 interrupts are encoded into two levels;
interrupt-controller; interrupt-controller;
#interrupt-cells = <3>; #interrupt-cells = <3>;
device_type = "interrupt-controller";
compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic"; compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
reg = <0x500 0x80>; reg = <0x500 0x80>;
}; };
timer@600 { // General Purpose Timer timer@600 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
cell-index = <0>;
reg = <0x600 0x10>; reg = <0x600 0x10>;
interrupts = <1 9 0>; interrupts = <1 9 0>;
interrupt-parent = <&mpc5200_pic>;
fsl,has-wdt; fsl,has-wdt;
}; };
timer@610 { // General Purpose Timer timer@610 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
cell-index = <1>;
reg = <0x610 0x10>; reg = <0x610 0x10>;
interrupts = <1 10 0>; interrupts = <1 10 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
timer@620 { // General Purpose Timer timer@620 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
cell-index = <2>;
reg = <0x620 0x10>; reg = <0x620 0x10>;
interrupts = <1 11 0>; interrupts = <1 11 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
timer@630 { // General Purpose Timer timer@630 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
cell-index = <3>;
reg = <0x630 0x10>; reg = <0x630 0x10>;
interrupts = <1 12 0>; interrupts = <1 12 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
timer@640 { // General Purpose Timer timer@640 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
cell-index = <4>;
reg = <0x640 0x10>; reg = <0x640 0x10>;
interrupts = <1 13 0>; interrupts = <1 13 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
timer@650 { // General Purpose Timer timer@650 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
cell-index = <5>;
reg = <0x650 0x10>; reg = <0x650 0x10>;
interrupts = <1 14 0>; interrupts = <1 14 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
timer@660 { // General Purpose Timer timer@660 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
cell-index = <6>;
reg = <0x660 0x10>; reg = <0x660 0x10>;
interrupts = <1 15 0>; interrupts = <1 15 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
timer@670 { // General Purpose Timer timer@670 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
cell-index = <7>;
reg = <0x670 0x10>; reg = <0x670 0x10>;
interrupts = <1 16 0>; interrupts = <1 16 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
rtc@800 { // Real time clock rtc@800 { // Real time clock
compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc"; compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
reg = <0x800 0x100>; reg = <0x800 0x100>;
interrupts = <1 5 0 1 6 0>; interrupts = <1 5 0 1 6 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
can@900 { can@900 {
compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan"; compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
cell-index = <0>;
interrupts = <2 17 0>; interrupts = <2 17 0>;
interrupt-parent = <&mpc5200_pic>;
reg = <0x900 0x80>; reg = <0x900 0x80>;
}; };
can@980 { can@980 {
compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan"; compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
cell-index = <1>;
interrupts = <2 18 0>; interrupts = <2 18 0>;
interrupt-parent = <&mpc5200_pic>;
reg = <0x980 0x80>; reg = <0x980 0x80>;
}; };
gpio@b00 { gpio_simple: gpio@b00 {
compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio"; compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
reg = <0xb00 0x40>; reg = <0xb00 0x40>;
interrupts = <1 7 0>; interrupts = <1 7 0>;
interrupt-parent = <&mpc5200_pic>; gpio-controller;
#gpio-cells = <2>;
}; };
gpio@c00 { gpio_wkup: gpio@c00 {
compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup"; compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
reg = <0xc00 0x40>; reg = <0xc00 0x40>;
interrupts = <1 8 0 0 3 0>; interrupts = <1 8 0 0 3 0>;
interrupt-parent = <&mpc5200_pic>; gpio-controller;
#gpio-cells = <2>;
}; };
spi@f00 { spi@f00 {
compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi"; compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
reg = <0xf00 0x20>; reg = <0xf00 0x20>;
interrupts = <2 13 0 2 14 0>; interrupts = <2 13 0 2 14 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
usb@1000 { usb@1000 {
compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be"; compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
reg = <0x1000 0xff>; reg = <0x1000 0xff>;
interrupts = <2 6 0>; interrupts = <2 6 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
dma-controller@1200 { dma-controller@1200 {
device_type = "dma-controller";
compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm"; compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
reg = <0x1200 0x80>; reg = <0x1200 0x80>;
interrupts = <3 0 0 3 1 0 3 2 0 3 3 0 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
3 4 0 3 5 0 3 6 0 3 7 0 3 4 0 3 5 0 3 6 0 3 7 0
3 8 0 3 9 0 3 10 0 3 11 0 3 8 0 3 9 0 3 10 0 3 11 0
3 12 0 3 13 0 3 14 0 3 15 0>; 3 12 0 3 13 0 3 14 0 3 15 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
xlb@1f00 { xlb@1f00 {
...@@ -196,13 +173,10 @@ xlb@1f00 { ...@@ -196,13 +173,10 @@ xlb@1f00 {
}; };
serial@2000 { // PSC1 serial@2000 { // PSC1
device_type = "serial";
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
port-number = <0>; // Logical port assignment
cell-index = <0>; cell-index = <0>;
reg = <0x2000 0x100>; reg = <0x2000 0x100>;
interrupts = <2 1 0>; interrupts = <2 1 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
// PSC2 in ac97 mode example // PSC2 in ac97 mode example
...@@ -211,7 +185,6 @@ serial@2000 { // PSC1 ...@@ -211,7 +185,6 @@ serial@2000 { // PSC1
// cell-index = <1>; // cell-index = <1>;
// reg = <0x2200 0x100>; // reg = <0x2200 0x100>;
// interrupts = <2 2 0>; // interrupts = <2 2 0>;
// interrupt-parent = <&mpc5200_pic>;
//}; //};
// PSC3 in CODEC mode example // PSC3 in CODEC mode example
...@@ -220,27 +193,22 @@ serial@2000 { // PSC1 ...@@ -220,27 +193,22 @@ serial@2000 { // PSC1
// cell-index = <2>; // cell-index = <2>;
// reg = <0x2400 0x100>; // reg = <0x2400 0x100>;
// interrupts = <2 3 0>; // interrupts = <2 3 0>;
// interrupt-parent = <&mpc5200_pic>;
//}; //};
// PSC4 in uart mode example // PSC4 in uart mode example
//serial@2600 { // PSC4 //serial@2600 { // PSC4
// device_type = "serial";
// compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; // compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
// cell-index = <3>; // cell-index = <3>;
// reg = <0x2600 0x100>; // reg = <0x2600 0x100>;
// interrupts = <2 11 0>; // interrupts = <2 11 0>;
// interrupt-parent = <&mpc5200_pic>;
//}; //};
// PSC5 in uart mode example // PSC5 in uart mode example
//serial@2800 { // PSC5 //serial@2800 { // PSC5
// device_type = "serial";
// compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; // compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
// cell-index = <4>; // cell-index = <4>;
// reg = <0x2800 0x100>; // reg = <0x2800 0x100>;
// interrupts = <2 12 0>; // interrupts = <2 12 0>;
// interrupt-parent = <&mpc5200_pic>;
//}; //};
// PSC6 in spi mode example // PSC6 in spi mode example
...@@ -249,49 +217,40 @@ serial@2000 { // PSC1 ...@@ -249,49 +217,40 @@ serial@2000 { // PSC1
// cell-index = <5>; // cell-index = <5>;
// reg = <0x2c00 0x100>; // reg = <0x2c00 0x100>;
// interrupts = <2 4 0>; // interrupts = <2 4 0>;
// interrupt-parent = <&mpc5200_pic>;
//}; //};
ethernet@3000 { ethernet@3000 {
device_type = "network";
compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec"; compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
reg = <0x3000 0x400>; reg = <0x3000 0x400>;
local-mac-address = [ 00 00 00 00 00 00 ]; local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <2 5 0>; interrupts = <2 5 0>;
interrupt-parent = <&mpc5200_pic>;
phy-handle = <&phy0>; phy-handle = <&phy0>;
}; };
mdio@3000 { mdio@3000 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
compatible = "fsl,mpc5200b-mdio", "fsl,mpc5200-mdio"; compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co. interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
interrupt-parent = <&mpc5200_pic>;
phy0: ethernet-phy@0 { phy0: ethernet-phy@0 {
device_type = "ethernet-phy";
reg = <0>; reg = <0>;
}; };
}; };
ata@3a00 { ata@3a00 {
device_type = "ata";
compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata"; compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
reg = <0x3a00 0x100>; reg = <0x3a00 0x100>;
interrupts = <2 7 0>; interrupts = <2 7 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
i2c@3d00 { i2c@3d00 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
cell-index = <0>;
reg = <0x3d00 0x40>; reg = <0x3d00 0x40>;
interrupts = <2 15 0>; interrupts = <2 15 0>;
interrupt-parent = <&mpc5200_pic>;
fsl5200-clocking; fsl5200-clocking;
}; };
...@@ -299,14 +258,13 @@ i2c@3d40 { ...@@ -299,14 +258,13 @@ i2c@3d40 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
cell-index = <1>;
reg = <0x3d40 0x40>; reg = <0x3d40 0x40>;
interrupts = <2 16 0>; interrupts = <2 16 0>;
interrupt-parent = <&mpc5200_pic>;
fsl5200-clocking; fsl5200-clocking;
}; };
sram@8000 { sram@8000 {
compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram","sram"; compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
reg = <0x8000 0x4000>; reg = <0x8000 0x4000>;
}; };
}; };
...@@ -330,7 +288,6 @@ pci@f0000d00 { ...@@ -330,7 +288,6 @@ pci@f0000d00 {
0xc800 0 0 4 &mpc5200_pic 0 0 3>; 0xc800 0 0 4 &mpc5200_pic 0 0 3>;
clock-frequency = <0>; // From boot loader clock-frequency = <0>; // From boot loader
interrupts = <2 8 0 2 9 0 2 10 0>; interrupts = <2 8 0 2 9 0 2 10 0>;
interrupt-parent = <&mpc5200_pic>;
bus-range = <0 0>; bus-range = <0 0>;
ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000 ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000
0x02000000 0 0xa0000000 0xa0000000 0 0x10000000 0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
......
arch/powerpc/boot/dts/motionpro.dts
View file @ b8842451
...@@ -17,6 +17,7 @@ / { ...@@ -17,6 +17,7 @@ / {
compatible = "promess,motionpro"; compatible = "promess,motionpro";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
interrupt-parent = <&mpc5200_pic>;
cpus { cpus {
#address-cells = <1>; #address-cells = <1>;
...@@ -66,7 +67,6 @@ timer@600 { // General Purpose Timer ...@@ -66,7 +67,6 @@ timer@600 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
reg = <0x600 0x10>; reg = <0x600 0x10>;
interrupts = <1 9 0>; interrupts = <1 9 0>;
interrupt-parent = <&mpc5200_pic>;
fsl,has-wdt; fsl,has-wdt;
}; };
...@@ -74,35 +74,30 @@ timer@610 { // General Purpose Timer ...@@ -74,35 +74,30 @@ timer@610 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
reg = <0x610 0x10>; reg = <0x610 0x10>;
interrupts = <1 10 0>; interrupts = <1 10 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
timer@620 { // General Purpose Timer timer@620 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
reg = <0x620 0x10>; reg = <0x620 0x10>;
interrupts = <1 11 0>; interrupts = <1 11 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
timer@630 { // General Purpose Timer timer@630 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
reg = <0x630 0x10>; reg = <0x630 0x10>;
interrupts = <1 12 0>; interrupts = <1 12 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
timer@640 { // General Purpose Timer timer@640 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
reg = <0x640 0x10>; reg = <0x640 0x10>;
interrupts = <1 13 0>; interrupts = <1 13 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
timer@650 { // General Purpose Timer timer@650 { // General Purpose Timer
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
reg = <0x650 0x10>; reg = <0x650 0x10>;
interrupts = <1 14 0>; interrupts = <1 14 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
motionpro-led@660 { // Motion-PRO status LED motionpro-led@660 { // Motion-PRO status LED
...@@ -110,7 +105,6 @@ motionpro-led@660 { // Motion-PRO status LED ...@@ -110,7 +105,6 @@ motionpro-led@660 { // Motion-PRO status LED
label = "motionpro-statusled"; label = "motionpro-statusled";
reg = <0x660 0x10>; reg = <0x660 0x10>;
interrupts = <1 15 0>; interrupts = <1 15 0>;
interrupt-parent = <&mpc5200_pic>;
blink-delay = <100>; // 100 msec blink-delay = <100>; // 100 msec
}; };
...@@ -119,49 +113,46 @@ motionpro-led@670 { // Motion-PRO ready LED ...@@ -119,49 +113,46 @@ motionpro-led@670 { // Motion-PRO ready LED
label = "motionpro-readyled"; label = "motionpro-readyled";
reg = <0x670 0x10>; reg = <0x670 0x10>;
interrupts = <1 16 0>; interrupts = <1 16 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
rtc@800 { // Real time clock rtc@800 { // Real time clock
compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc"; compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
reg = <0x800 0x100>; reg = <0x800 0x100>;
interrupts = <1 5 0 1 6 0>; interrupts = <1 5 0 1 6 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
can@980 { can@980 {
compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan"; compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
interrupts = <2 18 0>; interrupts = <2 18 0>;
interrupt-parent = <&mpc5200_pic>;
reg = <0x980 0x80>; reg = <0x980 0x80>;
}; };
gpio@b00 { gpio_simple: gpio@b00 {
compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio"; compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
reg = <0xb00 0x40>; reg = <0xb00 0x40>;
interrupts = <1 7 0>; interrupts = <1 7 0>;
interrupt-parent = <&mpc5200_pic>; gpio-controller;
#gpio-cells = <2>;
}; };
gpio@c00 { gpio_wkup: gpio@c00 {
compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup"; compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
reg = <0xc00 0x40>; reg = <0xc00 0x40>;
interrupts = <1 8 0 0 3 0>; interrupts = <1 8 0 0 3 0>;
interrupt-parent = <&mpc5200_pic>; gpio-controller;
#gpio-cells = <2>;
}; };
spi@f00 { spi@f00 {
compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi"; compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
reg = <0xf00 0x20>; reg = <0xf00 0x20>;
interrupts = <2 13 0 2 14 0>; interrupts = <2 13 0 2 14 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
usb@1000 { usb@1000 {
compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be"; compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
reg = <0x1000 0xff>; reg = <0x1000 0xff>;
interrupts = <2 6 0>; interrupts = <2 6 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
dma-controller@1200 { dma-controller@1200 {
...@@ -171,7 +162,6 @@ dma-controller@1200 { ...@@ -171,7 +162,6 @@ dma-controller@1200 {
3 4 0 3 5 0 3 6 0 3 7 0 3 4 0 3 5 0 3 6 0 3 7 0
3 8 0 3 9 0 3 10 0 3 11 0 3 8 0 3 9 0 3 10 0 3 11 0
3 12 0 3 13 0 3 14 0 3 15 0>; 3 12 0 3 13 0 3 14 0 3 15 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
xlb@1f00 { xlb@1f00 {
...@@ -180,12 +170,9 @@ xlb@1f00 { ...@@ -180,12 +170,9 @@ xlb@1f00 {
}; };
serial@2000 { // PSC1 serial@2000 { // PSC1
device_type = "serial";
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
port-number = <0>; // Logical port assignment
reg = <0x2000 0x100>; reg = <0x2000 0x100>;
interrupts = <2 1 0>; interrupts = <2 1 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
// PSC2 in spi master mode // PSC2 in spi master mode
...@@ -194,26 +181,20 @@ spi@2200 { // PSC2 ...@@ -194,26 +181,20 @@ spi@2200 { // PSC2
cell-index = <1>; cell-index = <1>;
reg = <0x2200 0x100>; reg = <0x2200 0x100>;
interrupts = <2 2 0>; interrupts = <2 2 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
// PSC5 in uart mode // PSC5 in uart mode
serial@2800 { // PSC5 serial@2800 { // PSC5
device_type = "serial";
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
port-number = <4>; // Logical port assignment
reg = <0x2800 0x100>; reg = <0x2800 0x100>;
interrupts = <2 12 0>; interrupts = <2 12 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
ethernet@3000 { ethernet@3000 {
device_type = "network";
compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec"; compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
reg = <0x3000 0x400>; reg = <0x3000 0x400>;
local-mac-address = [ 00 00 00 00 00 00 ]; local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <2 5 0>; interrupts = <2 5 0>;
interrupt-parent = <&mpc5200_pic>;
phy-handle = <&phy0>; phy-handle = <&phy0>;
}; };
...@@ -223,10 +204,8 @@ mdio@3000 { ...@@ -223,10 +204,8 @@ mdio@3000 {
compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio"; compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co. interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
interrupt-parent = <&mpc5200_pic>;
phy0: ethernet-phy@2 { phy0: ethernet-phy@2 {
device_type = "ethernet-phy";
reg = <2>; reg = <2>;
}; };
}; };
...@@ -235,7 +214,6 @@ ata@3a00 { ...@@ -235,7 +214,6 @@ ata@3a00 {
compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata"; compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
reg = <0x3a00 0x100>; reg = <0x3a00 0x100>;
interrupts = <2 7 0>; interrupts = <2 7 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
i2c@3d40 { i2c@3d40 {
...@@ -244,7 +222,6 @@ i2c@3d40 { ...@@ -244,7 +222,6 @@ i2c@3d40 {
compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
reg = <0x3d40 0x40>; reg = <0x3d40 0x40>;
interrupts = <2 16 0>; interrupts = <2 16 0>;
interrupt-parent = <&mpc5200_pic>;
fsl5200-clocking; fsl5200-clocking;
rtc@68 { rtc@68 {
...@@ -259,8 +236,8 @@ sram@8000 { ...@@ -259,8 +236,8 @@ sram@8000 {
}; };
}; };
lpb { localbus {
compatible = "fsl,lpb"; compatible = "fsl,mpc5200b-lpb","simple-bus";
#address-cells = <2>; #address-cells = <2>;
#size-cells = <1>; #size-cells = <1>;
ranges = <0 0 0xff000000 0x01000000 ranges = <0 0 0xff000000 0x01000000
...@@ -273,7 +250,6 @@ kollmorgen@1,0 { ...@@ -273,7 +250,6 @@ kollmorgen@1,0 {
compatible = "promess,motionpro-kollmorgen"; compatible = "promess,motionpro-kollmorgen";
reg = <1 0 0x10000>; reg = <1 0 0x10000>;
interrupts = <1 1 0>; interrupts = <1 1 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
// 8-bit board CPLD on LocalPlus Bus CS2 // 8-bit board CPLD on LocalPlus Bus CS2
......
arch/powerpc/boot/dts/pcm030.dts
View file @ b8842451
This diff is collapsed.
arch/powerpc/boot/dts/tqm5200.dts
View file @ b8842451
...@@ -17,6 +17,7 @@ / { ...@@ -17,6 +17,7 @@ / {
compatible = "tqc,tqm5200"; compatible = "tqc,tqm5200";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
interrupt-parent = <&mpc5200_pic>;
cpus { cpus {
#address-cells = <1>; #address-cells = <1>;
...@@ -66,36 +67,33 @@ timer@600 { // General Purpose Timer ...@@ -66,36 +67,33 @@ timer@600 { // General Purpose Timer
compatible = "fsl,mpc5200-gpt"; compatible = "fsl,mpc5200-gpt";
reg = <0x600 0x10>; reg = <0x600 0x10>;
interrupts = <1 9 0>; interrupts = <1 9 0>;
interrupt-parent = <&mpc5200_pic>;
fsl,has-wdt; fsl,has-wdt;
}; };
can@900 { can@900 {
compatible = "fsl,mpc5200-mscan"; compatible = "fsl,mpc5200-mscan";
interrupts = <2 17 0>; interrupts = <2 17 0>;
interrupt-parent = <&mpc5200_pic>;
reg = <0x900 0x80>; reg = <0x900 0x80>;
}; };
can@980 { can@980 {
compatible = "fsl,mpc5200-mscan"; compatible = "fsl,mpc5200-mscan";
interrupts = <2 18 0>; interrupts = <2 18 0>;
interrupt-parent = <&mpc5200_pic>;
reg = <0x980 0x80>; reg = <0x980 0x80>;
}; };
gpio@b00 { gpio_simple: gpio@b00 {
compatible = "fsl,mpc5200-gpio"; compatible = "fsl,mpc5200-gpio";
reg = <0xb00 0x40>; reg = <0xb00 0x40>;
interrupts = <1 7 0>; interrupts = <1 7 0>;
interrupt-parent = <&mpc5200_pic>; gpio-controller;
#gpio-cells = <2>;
}; };
usb@1000 { usb@1000 {
compatible = "fsl,mpc5200-ohci","ohci-be"; compatible = "fsl,mpc5200-ohci","ohci-be";
reg = <0x1000 0xff>; reg = <0x1000 0xff>;
interrupts = <2 6 0>; interrupts = <2 6 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
dma-controller@1200 { dma-controller@1200 {
...@@ -105,7 +103,6 @@ dma-controller@1200 { ...@@ -105,7 +103,6 @@ dma-controller@1200 {
3 4 0 3 5 0 3 6 0 3 7 0 3 4 0 3 5 0 3 6 0 3 7 0
3 8 0 3 9 0 3 10 0 3 11 0 3 8 0 3 9 0 3 10 0 3 11 0
3 12 0 3 13 0 3 14 0 3 15 0>; 3 12 0 3 13 0 3 14 0 3 15 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
xlb@1f00 { xlb@1f00 {
...@@ -114,39 +111,28 @@ xlb@1f00 { ...@@ -114,39 +111,28 @@ xlb@1f00 {
}; };
serial@2000 { // PSC1 serial@2000 { // PSC1
device_type = "serial";
compatible = "fsl,mpc5200-psc-uart"; compatible = "fsl,mpc5200-psc-uart";
port-number = <0>; // Logical port assignment
reg = <0x2000 0x100>; reg = <0x2000 0x100>;
interrupts = <2 1 0>; interrupts = <2 1 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
serial@2200 { // PSC2 serial@2200 { // PSC2
device_type = "serial";
compatible = "fsl,mpc5200-psc-uart"; compatible = "fsl,mpc5200-psc-uart";
port-number = <1>; // Logical port assignment
reg = <0x2200 0x100>; reg = <0x2200 0x100>;
interrupts = <2 2 0>; interrupts = <2 2 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
serial@2400 { // PSC3 serial@2400 { // PSC3
device_type = "serial";
compatible = "fsl,mpc5200-psc-uart"; compatible = "fsl,mpc5200-psc-uart";
port-number = <2>; // Logical port assignment
reg = <0x2400 0x100>; reg = <0x2400 0x100>;
interrupts = <2 3 0>; interrupts = <2 3 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
ethernet@3000 { ethernet@3000 {
device_type = "network";
compatible = "fsl,mpc5200-fec"; compatible = "fsl,mpc5200-fec";
reg = <0x3000 0x400>; reg = <0x3000 0x400>;
local-mac-address = [ 00 00 00 00 00 00 ]; local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <2 5 0>; interrupts = <2 5 0>;
interrupt-parent = <&mpc5200_pic>;
phy-handle = <&phy0>; phy-handle = <&phy0>;
}; };
...@@ -156,10 +142,8 @@ mdio@3000 { ...@@ -156,10 +142,8 @@ mdio@3000 {
compatible = "fsl,mpc5200-mdio"; compatible = "fsl,mpc5200-mdio";
reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co. interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
interrupt-parent = <&mpc5200_pic>;
phy0: ethernet-phy@0 { phy0: ethernet-phy@0 {
device_type = "ethernet-phy";
reg = <0>; reg = <0>;
}; };
}; };
...@@ -168,7 +152,6 @@ ata@3a00 { ...@@ -168,7 +152,6 @@ ata@3a00 {
compatible = "fsl,mpc5200-ata"; compatible = "fsl,mpc5200-ata";
reg = <0x3a00 0x100>; reg = <0x3a00 0x100>;
interrupts = <2 7 0>; interrupts = <2 7 0>;
interrupt-parent = <&mpc5200_pic>;
}; };
i2c@3d40 { i2c@3d40 {
...@@ -177,7 +160,6 @@ i2c@3d40 { ...@@ -177,7 +160,6 @@ i2c@3d40 {
compatible = "fsl,mpc5200-i2c","fsl-i2c"; compatible = "fsl,mpc5200-i2c","fsl-i2c";
reg = <0x3d40 0x40>; reg = <0x3d40 0x40>;
interrupts = <2 16 0>; interrupts = <2 16 0>;
interrupt-parent = <&mpc5200_pic>;
fsl5200-clocking; fsl5200-clocking;
rtc@68 { rtc@68 {
...@@ -192,9 +174,8 @@ sram@8000 { ...@@ -192,9 +174,8 @@ sram@8000 {
}; };
}; };
lpb { localbus {
model = "fsl,lpb"; compatible = "fsl,mpc5200-lpb","simple-bus";
compatible = "fsl,lpb";
#address-cells = <2>; #address-cells = <2>;
#size-cells = <1>; #size-cells = <1>;
ranges = <0 0 0xfc000000 0x02000000>; ranges = <0 0 0xfc000000 0x02000000>;
...@@ -223,7 +204,6 @@ pci@f0000d00 { ...@@ -223,7 +204,6 @@ pci@f0000d00 {
0xc000 0 0 4 &mpc5200_pic 0 0 3>; 0xc000 0 0 4 &mpc5200_pic 0 0 3>;
clock-frequency = <0>; // From boot loader clock-frequency = <0>; // From boot loader
interrupts = <2 8 0 2 9 0 2 10 0>; interrupts = <2 8 0 2 9 0 2 10 0>;
interrupt-parent = <&mpc5200_pic>;
bus-range = <0 0>; bus-range = <0 0>;
ranges = <0x42000000 0 0x80000000 0x80000000 0 0x10000000 ranges = <0x42000000 0 0x80000000 0x80000000 0 0x10000000
0x02000000 0 0x90000000 0x90000000 0 0x10000000 0x02000000 0 0x90000000 0x90000000 0 0x10000000
......
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