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Kirill Smelkov
linux
Commits
ba3b6d75
Commit
ba3b6d75
authored
Mar 17, 2014
by
Steven Miao
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bf54x: drop unuesd HOST status,control,timeout registers bit define macros
Signed-off-by:
Steven Miao
<
realmz6@gmail.com
>
parent
a0c1fb2e
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arch/blackfin/mach-bf548/include/mach/defBF544.h
arch/blackfin/mach-bf548/include/mach/defBF544.h
+0
-30
arch/blackfin/mach-bf548/include/mach/defBF547.h
arch/blackfin/mach-bf548/include/mach/defBF547.h
+0
-30
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arch/blackfin/mach-bf548/include/mach/defBF544.h
View file @
ba3b6d75
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@@ -601,36 +601,6 @@
#define GU_TRANS 0xff00
/* Transparent Color - G/U Component */
#define BV_TRANS 0xff0000
/* Transparent Color - B/V Component */
/* Bit masks for HOST_CONTROL */
#define HOST_EN 0x1
/* Host Enable */
#define HOST_END 0x2
/* Host Endianess */
#define DATA_SIZE 0x4
/* Data Size */
#define HOST_RST 0x8
/* Host Reset */
#define HRDY_OVR 0x20
/* Host Ready Override */
#define INT_MODE 0x40
/* Interrupt Mode */
#define BT_EN 0x80
/* Bus Timeout Enable */
#define EHW 0x100
/* Enable Host Write */
#define EHR 0x200
/* Enable Host Read */
#define BDR 0x400
/* Burst DMA Requests */
/* Bit masks for HOST_STATUS */
#define DMA_READY 0x1
/* DMA Ready */
#define FIFOFULL 0x2
/* FIFO Full */
#define FIFOEMPTY 0x4
/* FIFO Empty */
#define DMA_COMPLETE 0x8
/* DMA Complete */
#define HSHK 0x10
/* Host Handshake */
#define HSTIMEOUT 0x20
/* Host Timeout */
#define HIRQ 0x40
/* Host Interrupt Request */
#define ALLOW_CNFG 0x80
/* Allow New Configuration */
#define DMA_DIR 0x100
/* DMA Direction */
#define BTE 0x200
/* Bus Timeout Enabled */
/* Bit masks for HOST_TIMEOUT */
#define COUNT_TIMEOUT 0x7ff
/* Host Timeout count */
/* Bit masks for TIMER_ENABLE1 */
#define TIMEN8 0x1
/* Timer 8 Enable */
...
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arch/blackfin/mach-bf548/include/mach/defBF547.h
View file @
ba3b6d75
...
...
@@ -581,36 +581,6 @@
#define GU_TRANS 0xff00
/* Transparent Color - G/U Component */
#define BV_TRANS 0xff0000
/* Transparent Color - B/V Component */
/* Bit masks for HOST_CONTROL */
#define HOST_EN 0x1
/* Host Enable */
#define HOST_END 0x2
/* Host Endianess */
#define DATA_SIZE 0x4
/* Data Size */
#define HOST_RST 0x8
/* Host Reset */
#define HRDY_OVR 0x20
/* Host Ready Override */
#define INT_MODE 0x40
/* Interrupt Mode */
#define BT_EN 0x80
/* Bus Timeout Enable */
#define EHW 0x100
/* Enable Host Write */
#define EHR 0x200
/* Enable Host Read */
#define BDR 0x400
/* Burst DMA Requests */
/* Bit masks for HOST_STATUS */
#define DMA_READY 0x1
/* DMA Ready */
#define FIFOFULL 0x2
/* FIFO Full */
#define FIFOEMPTY 0x4
/* FIFO Empty */
#define DMA_COMPLETE 0x8
/* DMA Complete */
#define HSHK 0x10
/* Host Handshake */
#define HSTIMEOUT 0x20
/* Host Timeout */
#define HIRQ 0x40
/* Host Interrupt Request */
#define ALLOW_CNFG 0x80
/* Allow New Configuration */
#define DMA_DIR 0x100
/* DMA Direction */
#define BTE 0x200
/* Bus Timeout Enabled */
/* Bit masks for HOST_TIMEOUT */
#define COUNT_TIMEOUT 0x7ff
/* Host Timeout count */
/* Bit masks for KPAD_CTL */
#define KPAD_EN 0x1
/* Keypad Enable */
...
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