Commit ba504994 authored by Cyrille Pitchen's avatar Cyrille Pitchen Committed by David S. Miller

net: macb: replace macb_writel() call by queue_writel() to update queue ISR

macb_interrupt() should not use macb_writel(bp, ISR, <value>) but only
queue_writel(queue, ISR, <value>).

There is one IRQ and one set of {ISR, IER, IDR, IMR} [1] registers per
queue on gem hardware, though only queue0 is actually used for now to
receive frames: other queues can already be used to transmit frames.

The queue_readl() and queue_writel() helper macros are designed to access
the relevant IRQ registers.

[1]
ISR: Interrupt Status Register
IER: Interrupt Enable Register
IDR: Interrupt Disable Register
IMR: Interrupt Mask Register
Signed-off-by: default avatarCyrille Pitchen <cyrille.pitchen@atmel.com>
Fixes: bfbb92c4 ("net: macb: Handle the RXUBR interrupt on all devices")
Acked-by: default avatarNicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 7629d9c1
...@@ -1100,7 +1100,7 @@ static irqreturn_t macb_interrupt(int irq, void *dev_id) ...@@ -1100,7 +1100,7 @@ static irqreturn_t macb_interrupt(int irq, void *dev_id)
macb_writel(bp, NCR, ctrl | MACB_BIT(RE)); macb_writel(bp, NCR, ctrl | MACB_BIT(RE));
if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE) if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
macb_writel(bp, ISR, MACB_BIT(RXUBR)); queue_writel(queue, ISR, MACB_BIT(RXUBR));
} }
if (status & MACB_BIT(ISR_ROVR)) { if (status & MACB_BIT(ISR_ROVR)) {
......
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