Commit bb6897f1 authored by Alex Deucher's avatar Alex Deucher

drm/amdgpu/powerplay/smu7: enable mclk switching if monitors are synced

If DC has synced the displays, we can enable mclk switching to
save power.
Reviewed-by: default avatarEvan Quan <evan.quan@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 951e15c2
...@@ -2956,9 +2956,10 @@ static int smu7_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, ...@@ -2956,9 +2956,10 @@ static int smu7_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
if (hwmgr->display_config->num_display == 0) if (hwmgr->display_config->num_display == 0)
disable_mclk_switching = false; disable_mclk_switching = false;
else else
disable_mclk_switching = ((1 < hwmgr->display_config->num_display) || disable_mclk_switching = ((1 < hwmgr->display_config->num_display) &&
disable_mclk_switching_for_frame_lock || !hwmgr->display_config->multi_monitor_in_sync) ||
smu7_vblank_too_short(hwmgr, hwmgr->display_config->min_vblank_time)); disable_mclk_switching_for_frame_lock ||
smu7_vblank_too_short(hwmgr, hwmgr->display_config->min_vblank_time);
sclk = smu7_ps->performance_levels[0].engine_clock; sclk = smu7_ps->performance_levels[0].engine_clock;
mclk = smu7_ps->performance_levels[0].memory_clock; mclk = smu7_ps->performance_levels[0].memory_clock;
......
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