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Commit bba95227 authored by Konrad Dybcio's avatar Konrad Dybcio Committed by Bjorn Andersson
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arm64: dts: qcom: sm6350: Set up DDR & L3 scaling 

Add the CPU OPP tables including core frequency and L3 bus frequency.
The L3 throughput values were chosen by studying the frequencies
available in HW LUT and picking the highest one that's less than the
CPU frequency. DDR clock rates come from the vendor kernel.

Available values from the HW LUT:
300000000
556800000
652800000
806400000
844800000
940800000
1132800000
1209600000
1286400000
1401600000
1459200000
Signed-off-by: default avatarKonrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230104171643.1004054-3-konrad.dybcio@linaro.org
parent e17a8065
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arch/arm64/boot/dts/qcom/sm6350.dtsi
View file @ bba95227
......@@ -8,6 +8,8 @@
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/dma/qcom-gpi.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interconnect/qcom,icc.h>
#include <dt-bindings/interconnect/qcom,osm-l3.h>
#include <dt-bindings/interconnect/qcom,sm6350.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
......@@ -47,6 +49,10 @@ CPU0: cpu@0 {
dynamic-power-coefficient = <100>;
next-level-cache = <&L2_0>;
qcom,freq-domain = <&cpufreq_hw 0>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY
&clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
#cooling-cells = <2>;
L2_0: l2-cache {
compatible = "cache";
......@@ -68,6 +74,10 @@ CPU1: cpu@100 {
dynamic-power-coefficient = <100>;
next-level-cache = <&L2_100>;
qcom,freq-domain = <&cpufreq_hw 0>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY
&clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
#cooling-cells = <2>;
L2_100: l2-cache {
compatible = "cache";
......@@ -85,6 +95,10 @@ CPU2: cpu@200 {
dynamic-power-coefficient = <100>;
next-level-cache = <&L2_200>;
qcom,freq-domain = <&cpufreq_hw 0>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY
&clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
#cooling-cells = <2>;
L2_200: l2-cache {
compatible = "cache";
......@@ -102,6 +116,10 @@ CPU3: cpu@300 {
dynamic-power-coefficient = <100>;
next-level-cache = <&L2_300>;
qcom,freq-domain = <&cpufreq_hw 0>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY
&clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
#cooling-cells = <2>;
L2_300: l2-cache {
compatible = "cache";
......@@ -119,6 +137,10 @@ CPU4: cpu@400 {
dynamic-power-coefficient = <100>;
next-level-cache = <&L2_400>;
qcom,freq-domain = <&cpufreq_hw 0>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY
&clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
#cooling-cells = <2>;
L2_400: l2-cache {
compatible = "cache";
......@@ -136,6 +158,10 @@ CPU5: cpu@500 {
dynamic-power-coefficient = <100>;
next-level-cache = <&L2_500>;
qcom,freq-domain = <&cpufreq_hw 0>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY
&clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
#cooling-cells = <2>;
L2_500: l2-cache {
compatible = "cache";
......@@ -154,6 +180,10 @@ CPU6: cpu@600 {
dynamic-power-coefficient = <703>;
next-level-cache = <&L2_600>;
qcom,freq-domain = <&cpufreq_hw 1>;
operating-points-v2 = <&cpu6_opp_table>;
interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY
&clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
#cooling-cells = <2>;
L2_600: l2-cache {
compatible = "cache";
......@@ -171,6 +201,10 @@ CPU7: cpu@700 {
dynamic-power-coefficient = <703>;
next-level-cache = <&L2_700>;
qcom,freq-domain = <&cpufreq_hw 1>;
operating-points-v2 = <&cpu6_opp_table>;
interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY
&clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
#cooling-cells = <2>;
L2_700: l2-cache {
compatible = "cache";
......@@ -229,6 +263,112 @@ memory@80000000 {
reg = <0x0 0x80000000 0x0 0x0>;
};
cpu0_opp_table: opp-table-cpu0 {
compatible = "operating-points-v2";
opp-shared;
opp-300000000 {
opp-hz = /bits/ 64 <300000000>;
/* DDR: 4-wide, 2 channels, double data rate, L3: 16-wide, 2 channels */
opp-peak-kBps = <(200000 * 4 * 2 * 2) (300000 * 16 * 2)>;
};
opp-576000000 {
opp-hz = /bits/ 64 <576000000>;
opp-peak-kBps = <(547000 * 4 * 2 * 2) (556800 * 16 * 2)>;
};
opp-768000000 {
opp-hz = /bits/ 64 <768000000>;
opp-peak-kBps = <(768000 * 4 * 2 * 2) (652800 * 16 * 2)>;
};
opp-1017600000 {
opp-hz = /bits/ 64 <1017600000>;
opp-peak-kBps = <(1017000 * 4 * 2 * 2) (940800 * 16 * 2)>;
};
opp-1248000000 {
opp-hz = /bits/ 64 <1248000000>;
opp-peak-kBps = <(1017000 * 4 * 2 * 2) (1209600 * 16 * 2)>;
};
opp-1324800000 {
opp-hz = /bits/ 64 <1324800000>;
opp-peak-kBps = <(1017000 * 4 * 2 * 2) (1286400 * 16 * 2)>;
};
opp-1516800000 {
opp-hz = /bits/ 64 <1516800000>;
opp-peak-kBps = <(1353000 * 4 * 2 * 2) (1459200 * 16 * 2)>;
};
opp-1612800000 {
opp-hz = /bits/ 64 <1612800000>;
opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>;
};
opp-1708800000 {
opp-hz = /bits/ 64 <1708800000>;
opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>;
};
};
cpu6_opp_table: opp-table-cpu6 {
compatible = "operating-points-v2";
opp-shared;
opp-300000000 {
opp-hz = /bits/ 64 <300000000>;
opp-peak-kBps = <(200000 * 4 * 2 * 2) (300000 * 16 * 2)>;
};
opp-787200000 {
opp-hz = /bits/ 64 <787200000>;
opp-peak-kBps = <(768000 * 4 * 2 * 2) (652800 * 16 * 2)>;
};
opp-979200000 {
opp-hz = /bits/ 64 <979200000>;
opp-peak-kBps = <(768000 * 4 * 2 * 2) (940800 * 16 * 2)>;
};
opp-1036800000 {
opp-hz = /bits/ 64 <1036800000>;
opp-peak-kBps = <(1017000 * 4 * 2 * 2) (940800 * 16 * 2)>;
};
opp-1248000000 {
opp-hz = /bits/ 64 <1248000000>;
opp-peak-kBps = <(1017000 * 4 * 2 * 2) (1209600 * 16 * 2)>;
};
opp-1401600000 {
opp-hz = /bits/ 64 <1401600000>;
opp-peak-kBps = <(1353000 * 4 * 2 * 2) (1401600 * 16 * 2)>;
};
opp-1555200000 {
opp-hz = /bits/ 64 <1555200000>;
opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>;
};
opp-1766400000 {
opp-hz = /bits/ 64 <1766400000>;
opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>;
};
opp-1900800000 {
opp-hz = /bits/ 64 <1900800000>;
opp-peak-kBps = <(1804000 * 4 * 2 * 2) (1459200 * 16 * 2)>;
};
opp-2073600000 {
opp-hz = /bits/ 64 <2073600000>;
opp-peak-kBps = <(2092000 * 4 * 2 * 2) (1459200 * 16 * 2)>;
};
};
pmu {
compatible = "arm,armv8-pmuv3";
interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_LOW>;
......
arch/arm64/boot/dts/qcom/sm7225.dtsi
View file @ bba95227
......@@ -14,3 +14,22 @@
&CPU5 { compatible = "qcom,kryo570"; };
&CPU6 { compatible = "qcom,kryo570"; };
&CPU7 { compatible = "qcom,kryo570"; };
&cpu0_opp_table {
opp-1804800000 {
opp-hz = /bits/ 64 <1804800000>;
opp-peak-kBps = <(1804000 * 4 * 2 * 2) (1459200 * 16 * 2)>;
};
};
&cpu6_opp_table {
opp-2131200000 {
opp-hz = /bits/ 64 <2131200000>;
opp-peak-kBps = <(2092000 * 4 * 2 * 2) (1459200 * 16 * 2)>;
};
opp-2208000000 {
opp-hz = /bits/ 64 <2208000000>;
opp-peak-kBps = <(2092000 * 4 * 2 * 2) (1459200 * 16 * 2)>;
};
};
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