Commit bbd73c02 authored by Ludovic Desroches's avatar Ludovic Desroches Committed by Alexandre Belloni

ARM: dts: at91: sama5d2: set the sdmmc gclk frequency

Set the frequency of the generated clock used by sdmmc devices in order
to not rely on the configuration done by previous components.
Signed-off-by: default avatarLudovic Desroches <ludovic.desroches@microchip.com>
Link: https://lore.kernel.org/r/20191128074522.69706-3-ludovic.desroches@microchip.comSigned-off-by: default avatarAlexandre Belloni <alexandre.belloni@bootlin.com>
parent e52a0336
......@@ -300,6 +300,8 @@ sdmmc0: sdio-host@a0000000 {
interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 31>, <&pmc PMC_TYPE_GCK 31>, <&pmc PMC_TYPE_CORE PMC_MAIN>;
clock-names = "hclock", "multclk", "baseclk";
assigned-clocks = <&pmc PMC_TYPE_GCK 31>;
assigned-clock-rates = <480000000>;
status = "disabled";
};
......@@ -309,6 +311,8 @@ sdmmc1: sdio-host@b0000000 {
interrupts = <32 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 32>, <&pmc PMC_TYPE_GCK 32>, <&pmc PMC_TYPE_CORE PMC_MAIN>;
clock-names = "hclock", "multclk", "baseclk";
assigned-clocks = <&pmc PMC_TYPE_GCK 32>;
assigned-clock-rates = <480000000>;
status = "disabled";
};
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment