Commit bc1fc64f authored by Mark Rustad's avatar Mark Rustad Committed by Jeff Kirsher

ixgbe: Fix FCRTH value in VM-to-VM loopback mode

The 82599 and X540 datasheets require that FCRTH be "set" for Tx
switching (VM-to-VM loopback) but it did not previously specify what
the value should be set to. It has now been determined that
the correct value is RXPBSIZE - (24*1024).

This setting is also required for later devices.
Signed-off-by: default avatarMark Rustad <mark.d.rustad@intel.com>
Signed-off-by: default avatarJeff Kirsher <jeffrey.t.kirsher@intel.com>
parent 3507a9b8
...@@ -2164,10 +2164,11 @@ s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw) ...@@ -2164,10 +2164,11 @@ s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw)
/* /*
* In order to prevent Tx hangs when the internal Tx * In order to prevent Tx hangs when the internal Tx
* switch is enabled we must set the high water mark * switch is enabled we must set the high water mark
* to the maximum FCRTH value. This allows the Tx * to the Rx packet buffer size - 24KB. This allows
* switch to function even under heavy Rx workloads. * the Tx switch to function even under heavy Rx
* workloads.
*/ */
fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 32; fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 24576;
} }
IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth); IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth);
......
...@@ -259,7 +259,13 @@ s32 ixgbe_dcb_config_pfc_82599(struct ixgbe_hw *hw, u8 pfc_en, u8 *prio_tc) ...@@ -259,7 +259,13 @@ s32 ixgbe_dcb_config_pfc_82599(struct ixgbe_hw *hw, u8 pfc_en, u8 *prio_tc)
fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE; fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;
IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl); IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl);
} else { } else {
reg = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 32; /* In order to prevent Tx hangs when the internal Tx
* switch is enabled we must set the high water mark
* to the Rx packet buffer size - 24KB. This allows
* the Tx switch to function even under heavy Rx
* workloads.
*/
reg = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 24576;
IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0); IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);
} }
......
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