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Commit be0c94ee authored by Ville Syrjälä's avatar Ville Syrjälä
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drm/i915: Split intel_cpu_transcoder_set_m_n() into M1/N1 vs. M2/N2 variants 

Make things a bit more explicit by splitting
intel_cpu_transcoder_set_m_n() into separate variants for M1/N1 vs.
M2/N2. Makes the DRRS M/N programming at least more obvious.

Note that for the MST and DRRS cases we don't need to call the
M2/N2 variant at all since the transcoders that support those
do not have the M2/N2 registers.

Same could be said for i9xx_crtc_enable() but I want to do a
higher level code sharing between that valleyview_crtc_enable()
later in which case we do need the M2/N2 variant. This is also
why I keep the transcoder_has_m2_n2() in intel_cpu_transcoder_set_m2_n2()
so the caller doesn't have necessarily care what the chosen
transcoder supports.
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220128103757.22461-5-ville.syrjala@linux.intel.comReviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
parent cc954cfa
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Showing with 54 additions and 45 deletions
drivers/gpu/drm/i915/display/intel_ddi.c
View file @ be0c94ee
......@@ -2510,9 +2510,10 @@ static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state,
if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
intel_ddi_set_dp_msa(crtc_state, conn_state);
intel_cpu_transcoder_set_m_n(crtc_state,
&crtc_state->dp_m_n,
&crtc_state->dp_m2_n2);
intel_cpu_transcoder_set_m1_n1(crtc_state,
&crtc_state->dp_m_n);
intel_cpu_transcoder_set_m2_n2(crtc_state,
&crtc_state->dp_m2_n2);
}
}
......
drivers/gpu/drm/i915/display/intel_display.c
View file @ be0c94ee
......@@ -1835,21 +1835,23 @@ static void ilk_crtc_enable(struct intel_atomic_state *state,
intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
if (intel_crtc_has_dp_encoder(new_crtc_state)) {
if (new_crtc_state->has_pch_encoder)
if (new_crtc_state->has_pch_encoder) {
intel_pch_transcoder_set_m_n(new_crtc_state,
&new_crtc_state->dp_m_n);
else
intel_cpu_transcoder_set_m_n(new_crtc_state,
&new_crtc_state->dp_m_n,
&new_crtc_state->dp_m2_n2);
} else {
intel_cpu_transcoder_set_m1_n1(new_crtc_state,
&new_crtc_state->dp_m_n);
intel_cpu_transcoder_set_m2_n2(new_crtc_state,
&new_crtc_state->dp_m2_n2);
}
}
intel_set_transcoder_timings(new_crtc_state);
intel_set_pipe_src_size(new_crtc_state);
if (new_crtc_state->has_pch_encoder)
intel_cpu_transcoder_set_m_n(new_crtc_state,
&new_crtc_state->fdi_m_n, NULL);
intel_cpu_transcoder_set_m1_n1(new_crtc_state,
&new_crtc_state->fdi_m_n);
ilk_set_pipeconf(new_crtc_state);
......@@ -2015,8 +2017,8 @@ static void hsw_configure_cpu_transcoder(const struct intel_crtc_state *crtc_sta
crtc_state->pixel_multiplier - 1);
if (crtc_state->has_pch_encoder)
intel_cpu_transcoder_set_m_n(crtc_state,
&crtc_state->fdi_m_n, NULL);
intel_cpu_transcoder_set_m1_n1(crtc_state,
&crtc_state->fdi_m_n);
hsw_set_frame_start_delay(crtc_state);
......@@ -2455,10 +2457,12 @@ static void valleyview_crtc_enable(struct intel_atomic_state *state,
if (drm_WARN_ON(&dev_priv->drm, crtc->active))
return;
if (intel_crtc_has_dp_encoder(new_crtc_state))
intel_cpu_transcoder_set_m_n(new_crtc_state,
&new_crtc_state->dp_m_n,
&new_crtc_state->dp_m2_n2);
if (intel_crtc_has_dp_encoder(new_crtc_state)) {
intel_cpu_transcoder_set_m1_n1(new_crtc_state,
&new_crtc_state->dp_m_n);
intel_cpu_transcoder_set_m2_n2(new_crtc_state,
&new_crtc_state->dp_m2_n2);
}
intel_set_transcoder_timings(new_crtc_state);
intel_set_pipe_src_size(new_crtc_state);
......@@ -2509,10 +2513,12 @@ static void i9xx_crtc_enable(struct intel_atomic_state *state,
if (drm_WARN_ON(&dev_priv->drm, crtc->active))
return;
if (intel_crtc_has_dp_encoder(new_crtc_state))
intel_cpu_transcoder_set_m_n(new_crtc_state,
&new_crtc_state->dp_m_n,
&new_crtc_state->dp_m2_n2);
if (intel_crtc_has_dp_encoder(new_crtc_state)) {
intel_cpu_transcoder_set_m1_n1(new_crtc_state,
&new_crtc_state->dp_m_n);
intel_cpu_transcoder_set_m2_n2(new_crtc_state,
&new_crtc_state->dp_m2_n2);
}
intel_set_transcoder_timings(new_crtc_state);
intel_set_pipe_src_size(new_crtc_state);
......@@ -3159,34 +3165,37 @@ static bool transcoder_has_m2_n2(struct drm_i915_private *dev_priv,
return DISPLAY_VER(dev_priv) == 7 || IS_CHERRYVIEW(dev_priv);
}
void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
const struct intel_link_m_n *m_n,
const struct intel_link_m_n *m2_n2)
void intel_cpu_transcoder_set_m1_n1(const struct intel_crtc_state *crtc_state,
const struct intel_link_m_n *m_n)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
enum transcoder transcoder = crtc_state->cpu_transcoder;
if (DISPLAY_VER(dev_priv) >= 5) {
if (DISPLAY_VER(dev_priv) >= 5)
intel_set_m_n(dev_priv, m_n,
PIPE_DATA_M1(transcoder), PIPE_DATA_N1(transcoder),
PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder));
/*
* M2_N2 registers are set only if DRRS is supported
* (to make sure the registers are not unnecessarily accessed).
*/
if (m2_n2 && crtc_state->has_drrs &&
transcoder_has_m2_n2(dev_priv, transcoder)) {
intel_set_m_n(dev_priv, m2_n2,
PIPE_DATA_M2(transcoder), PIPE_DATA_N2(transcoder),
PIPE_LINK_M2(transcoder), PIPE_LINK_N2(transcoder));
}
} else {
else
intel_set_m_n(dev_priv, m_n,
PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe),
PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe));
}
}
void intel_cpu_transcoder_set_m2_n2(const struct intel_crtc_state *crtc_state,
const struct intel_link_m_n *m_n)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum transcoder transcoder = crtc_state->cpu_transcoder;
if (!transcoder_has_m2_n2(dev_priv, transcoder))
return;
intel_set_m_n(dev_priv, m_n,
PIPE_DATA_M2(transcoder), PIPE_DATA_N2(transcoder),
PIPE_LINK_M2(transcoder), PIPE_LINK_N2(transcoder));
}
static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
......
drivers/gpu/drm/i915/display/intel_display.h
View file @ be0c94ee
......@@ -604,9 +604,10 @@ bool intel_fuzzy_clock_check(int clock1, int clock2);
void intel_display_prepare_reset(struct drm_i915_private *dev_priv);
void intel_display_finish_reset(struct drm_i915_private *dev_priv);
void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
const struct intel_link_m_n *m_n,
const struct intel_link_m_n *m2_n2);
void intel_cpu_transcoder_set_m1_n1(const struct intel_crtc_state *crtc_state,
const struct intel_link_m_n *m_n);
void intel_cpu_transcoder_set_m2_n2(const struct intel_crtc_state *crtc_state,
const struct intel_link_m_n *m_n);
void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
enum transcoder cpu_transcoder,
struct intel_link_m_n *m_n,
......
drivers/gpu/drm/i915/display/intel_dp_mst.c
View file @ be0c94ee
......@@ -523,9 +523,8 @@ static void intel_mst_pre_enable_dp(struct intel_atomic_state *state,
intel_ddi_set_dp_msa(pipe_config, conn_state);
intel_cpu_transcoder_set_m_n(pipe_config,
&pipe_config->dp_m_n,
&pipe_config->dp_m2_n2);
intel_cpu_transcoder_set_m1_n1(pipe_config,
&pipe_config->dp_m_n);
}
static void intel_mst_enable_dp(struct intel_atomic_state *state,
......
drivers/gpu/drm/i915/display/intel_drrs.c
View file @ be0c94ee
......@@ -115,9 +115,8 @@ static void
intel_drrs_set_refresh_rate_m_n(const struct intel_crtc_state *crtc_state,
enum drrs_refresh_rate_type refresh_type)
{
intel_cpu_transcoder_set_m_n(crtc_state, refresh_type == DRRS_LOW_RR ?
&crtc_state->dp_m2_n2 : &crtc_state->dp_m_n,
NULL);
intel_cpu_transcoder_set_m1_n1(crtc_state, refresh_type == DRRS_LOW_RR ?
&crtc_state->dp_m2_n2 : &crtc_state->dp_m_n);
}
static void intel_drrs_set_state(struct drm_i915_private *dev_priv,
......
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