Commit be215b92 authored by Martin Blumenstingl's avatar Martin Blumenstingl Committed by Kevin Hilman

dt-bindings: timer: meson6_timer: document the clock inputs

The Meson Timer IP has two clock inputs:
- pclk which is used as "system clock" timebase of Timer E
- xtal which is used for the 1us, 10us, 100us and 1ms timebases of Timer
  A, B, C, D and E

The IP block has four internal dividers (XTAL is running at 24MHz):
- "xtal div 24" for 1us resolution
- "xtal div 240" for 10us resolution
- "xtal div 2400" for 100us resolution
- "xtal div 24000" for 1ms resolution
Suggested-by: default avatarJianxin Pan <jianxin.pan@amlogic.com>
Signed-off-by: default avatarMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: default avatarKevin Hilman <khilman@baylibre.com>
parent e55b892e
...@@ -5,6 +5,8 @@ Required properties: ...@@ -5,6 +5,8 @@ Required properties:
- compatible : should be "amlogic,meson6-timer" - compatible : should be "amlogic,meson6-timer"
- reg : Specifies base physical address and size of the registers. - reg : Specifies base physical address and size of the registers.
- interrupts : The four interrupts, one for each timer event - interrupts : The four interrupts, one for each timer event
- clocks : phandles to the pclk (system clock) and XTAL clocks
- clock-names : must contain "pclk" and "xtal"
Example: Example:
...@@ -15,4 +17,6 @@ timer@c1109940 { ...@@ -15,4 +17,6 @@ timer@c1109940 {
<GIC_SPI 11 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 11 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 6 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 6 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 29 IRQ_TYPE_EDGE_RISING>; <GIC_SPI 29 IRQ_TYPE_EDGE_RISING>;
clocks = <&xtal>, <&clk81>;
clock-names = "xtal", "pclk";
}; };
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