Commit c00a19c8 authored by Amit Daniel Kachhap's avatar Amit Daniel Kachhap Committed by Russell King (Oracle)

ARM: 9268/1: vfp: Add hwcap FPHP and ASIMDHP for FEAT_FP16

Floating point half-precision (FPHP) and Advanced SIMD half-precision
(ASIMDHP) are VFP features (FEAT_FP16) represented by MVFR1 identification register. These capabilities can optionally exist with VFPv3 and mandatory with VFPv4. Both these new features exist for Armv8 architecture in AArch32 state.

These hwcaps may be useful for the userspace to add conditional check
before trying to use FEAT_FP16 feature specific instructions.
Reviewed-by: default avatarLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: default avatarAmit Daniel Kachhap <amit.kachhap@arm.com>
Signed-off-by: default avatarRussell King (Oracle) <rmk+kernel@armlinux.org.uk>
parent 74c344e6
...@@ -87,6 +87,12 @@ ...@@ -87,6 +87,12 @@
#define MVFR0_DP_BIT (8) #define MVFR0_DP_BIT (8)
#define MVFR0_DP_MASK (0xf << MVFR0_DP_BIT) #define MVFR0_DP_MASK (0xf << MVFR0_DP_BIT)
/* MVFR1 bits */
#define MVFR1_ASIMDHP_BIT (20)
#define MVFR1_ASIMDHP_MASK (0xf << MVFR1_ASIMDHP_BIT)
#define MVFR1_FPHP_BIT (24)
#define MVFR1_FPHP_MASK (0xf << MVFR1_FPHP_BIT)
/* Bit patterns for decoding the packaged operation descriptors */ /* Bit patterns for decoding the packaged operation descriptors */
#define VFPOPDESC_LENGTH_BIT (9) #define VFPOPDESC_LENGTH_BIT (9)
#define VFPOPDESC_LENGTH_MASK (0x07 << VFPOPDESC_LENGTH_BIT) #define VFPOPDESC_LENGTH_MASK (0x07 << VFPOPDESC_LENGTH_BIT)
......
...@@ -28,6 +28,8 @@ ...@@ -28,6 +28,8 @@
#define HWCAP_IDIV (HWCAP_IDIVA | HWCAP_IDIVT) #define HWCAP_IDIV (HWCAP_IDIVA | HWCAP_IDIVT)
#define HWCAP_LPAE (1 << 20) #define HWCAP_LPAE (1 << 20)
#define HWCAP_EVTSTRM (1 << 21) #define HWCAP_EVTSTRM (1 << 21)
#define HWCAP_FPHP (1 << 22)
#define HWCAP_ASIMDHP (1 << 23)
/* /*
* HWCAP2 flags - for elf_hwcap2 (in kernel) and AT_HWCAP2 * HWCAP2 flags - for elf_hwcap2 (in kernel) and AT_HWCAP2
......
...@@ -1249,6 +1249,8 @@ static const char *hwcap_str[] = { ...@@ -1249,6 +1249,8 @@ static const char *hwcap_str[] = {
"vfpd32", "vfpd32",
"lpae", "lpae",
"evtstrm", "evtstrm",
"fphp",
"asimdhp",
NULL NULL
}; };
......
...@@ -831,6 +831,10 @@ static int __init vfp_init(void) ...@@ -831,6 +831,10 @@ static int __init vfp_init(void)
if ((fmrx(MVFR1) & 0xf0000000) == 0x10000000) if ((fmrx(MVFR1) & 0xf0000000) == 0x10000000)
elf_hwcap |= HWCAP_VFPv4; elf_hwcap |= HWCAP_VFPv4;
if (((fmrx(MVFR1) & MVFR1_ASIMDHP_MASK) >> MVFR1_ASIMDHP_BIT) == 0x2)
elf_hwcap |= HWCAP_ASIMDHP;
if (((fmrx(MVFR1) & MVFR1_FPHP_MASK) >> MVFR1_FPHP_BIT) == 0x3)
elf_hwcap |= HWCAP_FPHP;
} }
/* Extract the architecture version on pre-cpuid scheme */ /* Extract the architecture version on pre-cpuid scheme */
} else { } else {
......
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