Commit c0879ed6 authored by Fabrice Gasnier's avatar Fabrice Gasnier Committed by Jonathan Cameron

dt-bindings: iio: adc: stm32-dfsdm: fix types, add missing pinctrl

- Add missing pinctrl description. Support is made optional as dfsdm
  may use internal sources (e.g. via registers)
- Fix typo in IIO STM32 DFSDM filter "MANCH_F" description.
Basically, this should be "falling edge = logic 0", not "1" that applies
to "MANCH_R".
BTW, make the description complete by describing both rising/falling
edges as described in reference manuals.

Fixes: 6c82f947 ("IIO: add DT bindings for stm32 DFSDM filter")
Signed-off-by: default avatarFabrice Gasnier <fabrice.gasnier@st.com>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarJonathan Cameron <Jonathan.Cameron@huawei.com>
parent 0dad1ece
......@@ -32,6 +32,10 @@ Optional properties:
to "clock" property. Frequency must be a multiple of the rcc
clock frequency. If not, SPI CLKOUT frequency will not be
accurate.
- pinctrl-names: Set to "default".
- pinctrl-0: List of phandles pointing to pin configuration
nodes to set pins in mode of operation for dfsdm
on external pin.
Contents of a STM32 DFSDM child nodes:
--------------------------------------
......@@ -68,8 +72,8 @@ Optional properties:
- st,adc-channel-types: Single-ended channel input type.
- "SPI_R": SPI with data on rising edge (default)
- "SPI_F": SPI with data on falling edge
- "MANCH_R": manchester codec, rising edge = logic 0
- "MANCH_F": manchester codec, falling edge = logic 1
- "MANCH_R": manchester codec, rising edge = logic 0, falling edge = logic 1
- "MANCH_F": manchester codec, rising edge = logic 1, falling edge = logic 0
- st,adc-channel-clk-src: Conversion clock source.
- "CLKIN": external SPI clock (CLKIN x)
- "CLKOUT": internal SPI clock (CLKOUT) (default)
......
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