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Commit c11ffe52 authored by Ian Rogers's avatar Ian Rogers Committed by Arnaldo Carvalho de Melo
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perf vendor events: Update for Westmere EP-DP 

Events are still at version 2:
    https://download.01.org/perfmon/WSM-EP-DP
Json files generated by the latest code at:
    https://github.com/intel/event-converter-for-linux-perf

Tested:

  ...
    6: Parse event definition strings                                  : Ok
    7: Simple expression parser                                        : Ok
  ...
    9: Parse perf pmu format                                           : Ok
   10: PMU events                                                      :
   10.1: PMU event table sanity                                        : Ok
   10.2: PMU event map aliases                                         : Ok
   10.3: Parsing of PMU event table metrics                            : Ok
   10.4: Parsing of PMU event table metrics with fake PMUs             : Ok
  ...
   68: Parse and process metrics                                       : Ok
  ...
   88: perf stat metrics (shadow stat) test                            : Ok
   89: perf all metricgroups test                                      : Ok
   90: perf all metrics test                                           : Ok
   91: perf all PMU test                                               : Ok
  ...
Reviewed-by: default avatarKan Liang <kan.liang@linux.intel.com>
Signed-off-by: default avatarIan Rogers <irogers@google.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: James Clark <james.clark@arm.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.garry@huawei.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Zhengjun Xing <zhengjun.xing@linux.intel.com>
Link: https://lore.kernel.org/r/20220201015858.1226914-8-irogers@google.comSigned-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
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tools/perf/pmu-events/arch/x86/westmereep-dp/cache.json
View file @ c11ffe52
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tools/perf/pmu-events/arch/x86/westmereep-dp/frontend.json
View file @ c11ffe52
[
{
"EventCode": "0xD0",
"BriefDescription": "Instructions decoded",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventCode": "0xD0",
"EventName": "MACRO_INSTS.DECODED",
"SampleAfterValue": "2000000",
"BriefDescription": "Instructions decoded"
"UMask": "0x1"
},
{
"EventCode": "0xA6",
"BriefDescription": "Macro-fused instructions decoded",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventCode": "0xA6",
"EventName": "MACRO_INSTS.FUSIONS_DECODED",
"SampleAfterValue": "2000000",
"BriefDescription": "Macro-fused instructions decoded"
"UMask": "0x1"
},
{
"EventCode": "0x19",
"BriefDescription": "Two Uop instructions decoded",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventCode": "0x19",
"EventName": "TWO_UOP_INSTS_DECODED",
"SampleAfterValue": "2000000",
"BriefDescription": "Two Uop instructions decoded"
"UMask": "0x1"
}
]
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tools/perf/pmu-events/arch/x86/westmereep-dp/virtual-memory.json
View file @ c11ffe52
[
{
"EventCode": "0x8",
"BriefDescription": "DTLB load misses",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventCode": "0x8",
"EventName": "DTLB_LOAD_MISSES.ANY",
"SampleAfterValue": "200000",
"BriefDescription": "DTLB load misses"
"UMask": "0x1"
},
{
"EventCode": "0x8",
"BriefDescription": "DTLB load miss large page walks",
"Counter": "0,1,2,3",
"UMask": "0x80",
"EventCode": "0x8",
"EventName": "DTLB_LOAD_MISSES.LARGE_WALK_COMPLETED",
"SampleAfterValue": "200000",
"BriefDescription": "DTLB load miss large page walks"
"UMask": "0x80"
},
{
"EventCode": "0x8",
"BriefDescription": "DTLB load miss caused by low part of address",
"Counter": "0,1,2,3",
"UMask": "0x20",
"EventCode": "0x8",
"EventName": "DTLB_LOAD_MISSES.PDE_MISS",
"SampleAfterValue": "200000",
"BriefDescription": "DTLB load miss caused by low part of address"
"UMask": "0x20"
},
{
"EventCode": "0x8",
"BriefDescription": "DTLB second level hit",
"Counter": "0,1,2,3",
"UMask": "0x10",
"EventCode": "0x8",
"EventName": "DTLB_LOAD_MISSES.STLB_HIT",
"SampleAfterValue": "2000000",
"BriefDescription": "DTLB second level hit"
"UMask": "0x10"
},
{
"EventCode": "0x8",
"BriefDescription": "DTLB load miss page walks complete",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventCode": "0x8",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
"SampleAfterValue": "200000",
"BriefDescription": "DTLB load miss page walks complete"
"UMask": "0x2"
},
{
"EventCode": "0x8",
"BriefDescription": "DTLB load miss page walk cycles",
"Counter": "0,1,2,3",
"UMask": "0x4",
"EventCode": "0x8",
"EventName": "DTLB_LOAD_MISSES.WALK_CYCLES",
"SampleAfterValue": "200000",
"BriefDescription": "DTLB load miss page walk cycles"
"UMask": "0x4"
},
{
"EventCode": "0x49",
"BriefDescription": "DTLB misses",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventCode": "0x49",
"EventName": "DTLB_MISSES.ANY",
"SampleAfterValue": "200000",
"BriefDescription": "DTLB misses"
"UMask": "0x1"
},
{
"EventCode": "0x49",
"BriefDescription": "DTLB miss large page walks",
"Counter": "0,1,2,3",
"UMask": "0x80",
"EventCode": "0x49",
"EventName": "DTLB_MISSES.LARGE_WALK_COMPLETED",
"SampleAfterValue": "200000",
"BriefDescription": "DTLB miss large page walks"
"UMask": "0x80"
},
{
"EventCode": "0x49",
"BriefDescription": "DTLB misses casued by low part of address",
"Counter": "0,1,2,3",
"UMask": "0x20",
"EventCode": "0x49",
"EventName": "DTLB_MISSES.PDE_MISS",
"SampleAfterValue": "200000",
"BriefDescription": "DTLB misses casued by low part of address"
"UMask": "0x20"
},
{
"EventCode": "0x49",
"BriefDescription": "DTLB first level misses but second level hit",
"Counter": "0,1,2,3",
"UMask": "0x10",
"EventCode": "0x49",
"EventName": "DTLB_MISSES.STLB_HIT",
"SampleAfterValue": "200000",
"BriefDescription": "DTLB first level misses but second level hit"
"UMask": "0x10"
},
{
"EventCode": "0x49",
"BriefDescription": "DTLB miss page walks",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventCode": "0x49",
"EventName": "DTLB_MISSES.WALK_COMPLETED",
"SampleAfterValue": "200000",
"BriefDescription": "DTLB miss page walks"
"UMask": "0x2"
},
{
"EventCode": "0x49",
"BriefDescription": "DTLB miss page walk cycles",
"Counter": "0,1,2,3",
"UMask": "0x4",
"EventCode": "0x49",
"EventName": "DTLB_MISSES.WALK_CYCLES",
"SampleAfterValue": "2000000",
"BriefDescription": "DTLB miss page walk cycles"
"UMask": "0x4"
},
{
"EventCode": "0x4F",
"BriefDescription": "Extended Page Table walk cycles",
"Counter": "0,1,2,3",
"UMask": "0x10",
"EventCode": "0x4F",
"EventName": "EPT.WALK_CYCLES",
"SampleAfterValue": "2000000",
"BriefDescription": "Extended Page Table walk cycles"
"UMask": "0x10"
},
{
"EventCode": "0xAE",
"BriefDescription": "ITLB flushes",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventCode": "0xAE",
"EventName": "ITLB_FLUSH",
"SampleAfterValue": "2000000",
"BriefDescription": "ITLB flushes"
"UMask": "0x1"
},
{
"PEBS": "1",
"EventCode": "0xC8",
"BriefDescription": "ITLB miss",
"Counter": "0,1,2,3",
"UMask": "0x20",
"EventName": "ITLB_MISS_RETIRED",
"SampleAfterValue": "200000",
"BriefDescription": "Retired instructions that missed the ITLB (Precise Event)"
},
{
"EventCode": "0x85",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "ITLB_MISSES.ANY",
"SampleAfterValue": "200000",
"BriefDescription": "ITLB miss"
"UMask": "0x1"
},
{
"EventCode": "0x85",
"BriefDescription": "ITLB miss large page walks",
"Counter": "0,1,2,3",
"UMask": "0x80",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.LARGE_WALK_COMPLETED",
"SampleAfterValue": "200000",
"BriefDescription": "ITLB miss large page walks"
"UMask": "0x80"
},
{
"EventCode": "0x85",
"BriefDescription": "ITLB miss page walks",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED",
"SampleAfterValue": "200000",
"BriefDescription": "ITLB miss page walks"
"UMask": "0x2"
},
{
"EventCode": "0x85",
"BriefDescription": "ITLB miss page walk cycles",
"Counter": "0,1,2,3",
"UMask": "0x4",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_CYCLES",
"SampleAfterValue": "2000000",
"BriefDescription": "ITLB miss page walk cycles"
"UMask": "0x4"
},
{
"BriefDescription": "Retired instructions that missed the ITLB (Precise Event)",
"Counter": "0,1,2,3",
"EventCode": "0xC8",
"EventName": "ITLB_MISS_RETIRED",
"PEBS": "1",
"EventCode": "0xCB",
"SampleAfterValue": "200000",
"UMask": "0x20"
},
{
"BriefDescription": "Retired loads that miss the DTLB (Precise Event)",
"Counter": "0,1,2,3",
"UMask": "0x80",
"EventCode": "0xCB",
"EventName": "MEM_LOAD_RETIRED.DTLB_MISS",
"PEBS": "1",
"SampleAfterValue": "200000",
"BriefDescription": "Retired loads that miss the DTLB (Precise Event)"
"UMask": "0x80"
},
{
"PEBS": "1",
"EventCode": "0xC",
"BriefDescription": "Retired stores that miss the DTLB (Precise Event)",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventCode": "0xC",
"EventName": "MEM_STORE_RETIRED.DTLB_MISS",
"PEBS": "1",
"SampleAfterValue": "200000",
"BriefDescription": "Retired stores that miss the DTLB (Precise Event)"
"UMask": "0x1"
}
]
\ No newline at end of file
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