Commit c134c3ca authored by Isabel Zhang's avatar Isabel Zhang Committed by Alex Deucher

drm/amd/display: Add initialitions for PLL2 clock source

[Why]
Starting from 14nm, the PLL is built into the PHY and the PLL is mapped
to PHY on 1 to 1 basis. In the code, the DP port is mapped to a PLL that was not
initialized. This causes DP to HDMI dongle to not light up the display.

[How]
Initializations added for PLL2 when creating resources.
Signed-off-by: default avatarIsabel Zhang <isabel.zhang@amd.com>
Reviewed-by: default avatarEric Yang <eric.yang2@amd.com>
Acked-by: default avatarBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 6c81917a
...@@ -60,6 +60,7 @@ ...@@ -60,6 +60,7 @@
#include "dcn20/dcn20_dccg.h" #include "dcn20/dcn20_dccg.h"
#include "dcn21_hubbub.h" #include "dcn21_hubbub.h"
#include "dcn10/dcn10_resource.h" #include "dcn10/dcn10_resource.h"
#include "dce110/dce110_resource.h"
#include "dcn20/dcn20_dwb.h" #include "dcn20/dcn20_dwb.h"
#include "dcn20/dcn20_mmhubbub.h" #include "dcn20/dcn20_mmhubbub.h"
...@@ -856,6 +857,7 @@ static const struct dc_debug_options debug_defaults_diags = { ...@@ -856,6 +857,7 @@ static const struct dc_debug_options debug_defaults_diags = {
enum dcn20_clk_src_array_id { enum dcn20_clk_src_array_id {
DCN20_CLK_SRC_PLL0, DCN20_CLK_SRC_PLL0,
DCN20_CLK_SRC_PLL1, DCN20_CLK_SRC_PLL1,
DCN20_CLK_SRC_PLL2,
DCN20_CLK_SRC_TOTAL_DCN21 DCN20_CLK_SRC_TOTAL_DCN21
}; };
...@@ -1718,6 +1720,10 @@ static bool dcn21_resource_construct( ...@@ -1718,6 +1720,10 @@ static bool dcn21_resource_construct(
dcn21_clock_source_create(ctx, ctx->dc_bios, dcn21_clock_source_create(ctx, ctx->dc_bios,
CLOCK_SOURCE_COMBO_PHY_PLL1, CLOCK_SOURCE_COMBO_PHY_PLL1,
&clk_src_regs[1], false); &clk_src_regs[1], false);
pool->base.clock_sources[DCN20_CLK_SRC_PLL2] =
dcn21_clock_source_create(ctx, ctx->dc_bios,
CLOCK_SOURCE_COMBO_PHY_PLL2,
&clk_src_regs[2], false);
pool->base.clk_src_count = DCN20_CLK_SRC_TOTAL_DCN21; pool->base.clk_src_count = DCN20_CLK_SRC_TOTAL_DCN21;
......
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