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Commit c19829ba authored by Anup Patel's avatar Anup Patel Committed by Anup Patel
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KVM: riscv: selftests: Generate ISA extension reg_list using macros 

Various ISA extension reg_list have common pattern so let us generate
these using macros.

We define two macros for the above purpose:
1) KVM_ISA_EXT_SIMPLE_CONFIG - Macro to generate reg_list for
   ISA extension without any additional ONE_REG registers
2) KVM_ISA_EXT_SUBLIST_CONFIG - Macro to generate reg_list for
   ISA extension with additional ONE_REG registers

This patch also adds the missing config for svnapot.
Signed-off-by: default avatarAnup Patel <apatel@ventanamicro.com>
Reviewed-by: default avatarAndrew Jones <ajones@ventanamicro.com>
Signed-off-by: default avatarAnup Patel <anup@brainfault.org>
parent bcd08e9b
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Showing with 76 additions and 255 deletions
tools/testing/selftests/kvm/riscv/get-reg-list.c
View file @ c19829ba
...@@ -583,10 +583,6 @@ static __u64 base_skips_set[] = { ...@@ -583,10 +583,6 @@ static __u64 base_skips_set[] = {
KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_TIMER | KVM_REG_RISCV_TIMER_REG(state), KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_TIMER | KVM_REG_RISCV_TIMER_REG(state),
}; };
static __u64 h_regs[] = {
KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_H,
};
static __u64 zicbom_regs[] = { static __u64 zicbom_regs[] = {
KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CONFIG | KVM_REG_RISCV_CONFIG_REG(zicbom_block_size), KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CONFIG | KVM_REG_RISCV_CONFIG_REG(zicbom_block_size),
KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZICBOM, KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZICBOM,
...@@ -597,54 +593,6 @@ static __u64 zicboz_regs[] = { ...@@ -597,54 +593,6 @@ static __u64 zicboz_regs[] = {
KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZICBOZ, KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZICBOZ,
}; };
static __u64 svpbmt_regs[] = {
KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SVPBMT,
};
static __u64 sstc_regs[] = {
KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SSTC,
};
static __u64 svinval_regs[] = {
KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SVINVAL,
};
static __u64 zihintpause_regs[] = {
KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZIHINTPAUSE,
};
static __u64 zba_regs[] = {
KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZBA,
};
static __u64 zbb_regs[] = {
KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZBB,
};
static __u64 zbs_regs[] = {
KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZBS,
};
static __u64 zicntr_regs[] = {
KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZICNTR,
};
static __u64 zicond_regs[] = {
KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZICOND,
};
static __u64 zicsr_regs[] = {
KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZICSR,
};
static __u64 zifencei_regs[] = {
KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZIFENCEI,
};
static __u64 zihpm_regs[] = {
KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZIHPM,
};
static __u64 aia_regs[] = { static __u64 aia_regs[] = {
KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(siselect), KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(siselect),
KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(iprio1), KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(iprio1),
...@@ -735,221 +683,94 @@ static __u64 fp_d_regs[] = { ...@@ -735,221 +683,94 @@ static __u64 fp_d_regs[] = {
KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_D, KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_D,
}; };
#define BASE_SUBLIST \ #define SUBLIST_BASE \
{"base", .regs = base_regs, .regs_n = ARRAY_SIZE(base_regs), \ {"base", .regs = base_regs, .regs_n = ARRAY_SIZE(base_regs), \
.skips_set = base_skips_set, .skips_set_n = ARRAY_SIZE(base_skips_set),} .skips_set = base_skips_set, .skips_set_n = ARRAY_SIZE(base_skips_set),}
#define H_REGS_SUBLIST \ #define SUBLIST_ZICBOM \
{"h", .feature = KVM_RISCV_ISA_EXT_H, .regs = h_regs, .regs_n = ARRAY_SIZE(h_regs),}
#define ZICBOM_REGS_SUBLIST \
{"zicbom", .feature = KVM_RISCV_ISA_EXT_ZICBOM, .regs = zicbom_regs, .regs_n = ARRAY_SIZE(zicbom_regs),} {"zicbom", .feature = KVM_RISCV_ISA_EXT_ZICBOM, .regs = zicbom_regs, .regs_n = ARRAY_SIZE(zicbom_regs),}
#define ZICBOZ_REGS_SUBLIST \ #define SUBLIST_ZICBOZ \
{"zicboz", .feature = KVM_RISCV_ISA_EXT_ZICBOZ, .regs = zicboz_regs, .regs_n = ARRAY_SIZE(zicboz_regs),} {"zicboz", .feature = KVM_RISCV_ISA_EXT_ZICBOZ, .regs = zicboz_regs, .regs_n = ARRAY_SIZE(zicboz_regs),}
#define SVPBMT_REGS_SUBLIST \ #define SUBLIST_AIA \
{"svpbmt", .feature = KVM_RISCV_ISA_EXT_SVPBMT, .regs = svpbmt_regs, .regs_n = ARRAY_SIZE(svpbmt_regs),}
#define SSTC_REGS_SUBLIST \
{"sstc", .feature = KVM_RISCV_ISA_EXT_SSTC, .regs = sstc_regs, .regs_n = ARRAY_SIZE(sstc_regs),}
#define SVINVAL_REGS_SUBLIST \
{"svinval", .feature = KVM_RISCV_ISA_EXT_SVINVAL, .regs = svinval_regs, .regs_n = ARRAY_SIZE(svinval_regs),}
#define ZIHINTPAUSE_REGS_SUBLIST \
{"zihintpause", .feature = KVM_RISCV_ISA_EXT_ZIHINTPAUSE, .regs = zihintpause_regs, .regs_n = ARRAY_SIZE(zihintpause_regs),}
#define ZBA_REGS_SUBLIST \
{"zba", .feature = KVM_RISCV_ISA_EXT_ZBA, .regs = zba_regs, .regs_n = ARRAY_SIZE(zba_regs),}
#define ZBB_REGS_SUBLIST \
{"zbb", .feature = KVM_RISCV_ISA_EXT_ZBB, .regs = zbb_regs, .regs_n = ARRAY_SIZE(zbb_regs),}
#define ZBS_REGS_SUBLIST \
{"zbs", .feature = KVM_RISCV_ISA_EXT_ZBS, .regs = zbs_regs, .regs_n = ARRAY_SIZE(zbs_regs),}
#define ZICNTR_REGS_SUBLIST \
{"zicntr", .feature = KVM_RISCV_ISA_EXT_ZICNTR, .regs = zicntr_regs, .regs_n = ARRAY_SIZE(zicntr_regs),}
#define ZICOND_REGS_SUBLIST \
{"zicond", .feature = KVM_RISCV_ISA_EXT_ZICOND, .regs = zicond_regs, .regs_n = ARRAY_SIZE(zicond_regs),}
#define ZICSR_REGS_SUBLIST \
{"zicsr", .feature = KVM_RISCV_ISA_EXT_ZICSR, .regs = zicsr_regs, .regs_n = ARRAY_SIZE(zicsr_regs),}
#define ZIFENCEI_REGS_SUBLIST \
{"zifencei", .feature = KVM_RISCV_ISA_EXT_ZIFENCEI, .regs = zifencei_regs, .regs_n = ARRAY_SIZE(zifencei_regs),}
#define ZIHPM_REGS_SUBLIST \
{"zihpm", .feature = KVM_RISCV_ISA_EXT_ZIHPM, .regs = zihpm_regs, .regs_n = ARRAY_SIZE(zihpm_regs),}
#define AIA_REGS_SUBLIST \
{"aia", .feature = KVM_RISCV_ISA_EXT_SSAIA, .regs = aia_regs, .regs_n = ARRAY_SIZE(aia_regs),} {"aia", .feature = KVM_RISCV_ISA_EXT_SSAIA, .regs = aia_regs, .regs_n = ARRAY_SIZE(aia_regs),}
#define SMSTATEEN_REGS_SUBLIST \ #define SUBLIST_SMSTATEEN \
{"smstateen", .feature = KVM_RISCV_ISA_EXT_SMSTATEEN, .regs = smstateen_regs, .regs_n = ARRAY_SIZE(smstateen_regs),} {"smstateen", .feature = KVM_RISCV_ISA_EXT_SMSTATEEN, .regs = smstateen_regs, .regs_n = ARRAY_SIZE(smstateen_regs),}
#define FP_F_REGS_SUBLIST \ #define SUBLIST_FP_F \
{"fp_f", .feature = KVM_RISCV_ISA_EXT_F, .regs = fp_f_regs, \ {"fp_f", .feature = KVM_RISCV_ISA_EXT_F, .regs = fp_f_regs, \
.regs_n = ARRAY_SIZE(fp_f_regs),} .regs_n = ARRAY_SIZE(fp_f_regs),}
#define FP_D_REGS_SUBLIST \ #define SUBLIST_FP_D \
{"fp_d", .feature = KVM_RISCV_ISA_EXT_D, .regs = fp_d_regs, \ {"fp_d", .feature = KVM_RISCV_ISA_EXT_D, .regs = fp_d_regs, \
.regs_n = ARRAY_SIZE(fp_d_regs),} .regs_n = ARRAY_SIZE(fp_d_regs),}
static struct vcpu_reg_list h_config = { #define KVM_ISA_EXT_SIMPLE_CONFIG(ext, extu) \
.sublists = { static __u64 regs_##ext[] = { \
BASE_SUBLIST, KVM_REG_RISCV | KVM_REG_SIZE_ULONG | \
H_REGS_SUBLIST, KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_##extu, \
{0}, }; \
}, static struct vcpu_reg_list config_##ext = { \
}; .sublists = { \
SUBLIST_BASE, \
static struct vcpu_reg_list zicbom_config = { { \
.sublists = { .name = #ext, \
BASE_SUBLIST, .feature = KVM_RISCV_ISA_EXT_##extu, \
ZICBOM_REGS_SUBLIST, .regs = regs_##ext, \
{0}, .regs_n = ARRAY_SIZE(regs_##ext), \
}, }, \
}; {0}, \
}, \
static struct vcpu_reg_list zicboz_config = { } \
.sublists = {
BASE_SUBLIST, #define KVM_ISA_EXT_SUBLIST_CONFIG(ext, extu) \
ZICBOZ_REGS_SUBLIST, static struct vcpu_reg_list config_##ext = { \
{0}, .sublists = { \
}, SUBLIST_BASE, \
}; SUBLIST_##extu, \
{0}, \
static struct vcpu_reg_list svpbmt_config = { }, \
.sublists = { } \
BASE_SUBLIST,
SVPBMT_REGS_SUBLIST, /* Note: The below list is alphabetically sorted. */
{0},
}, KVM_ISA_EXT_SUBLIST_CONFIG(aia, AIA);
}; KVM_ISA_EXT_SUBLIST_CONFIG(fp_f, FP_F);
KVM_ISA_EXT_SUBLIST_CONFIG(fp_d, FP_D);
static struct vcpu_reg_list sstc_config = { KVM_ISA_EXT_SIMPLE_CONFIG(h, H);
.sublists = { KVM_ISA_EXT_SUBLIST_CONFIG(smstateen, SMSTATEEN);
BASE_SUBLIST, KVM_ISA_EXT_SIMPLE_CONFIG(sstc, SSTC);
SSTC_REGS_SUBLIST, KVM_ISA_EXT_SIMPLE_CONFIG(svinval, SVINVAL);
{0}, KVM_ISA_EXT_SIMPLE_CONFIG(svnapot, SVNAPOT);
}, KVM_ISA_EXT_SIMPLE_CONFIG(svpbmt, SVPBMT);
}; KVM_ISA_EXT_SIMPLE_CONFIG(zba, ZBA);
KVM_ISA_EXT_SIMPLE_CONFIG(zbb, ZBB);
static struct vcpu_reg_list svinval_config = { KVM_ISA_EXT_SIMPLE_CONFIG(zbs, ZBS);
.sublists = { KVM_ISA_EXT_SUBLIST_CONFIG(zicbom, ZICBOM);
BASE_SUBLIST, KVM_ISA_EXT_SUBLIST_CONFIG(zicboz, ZICBOZ);
SVINVAL_REGS_SUBLIST, KVM_ISA_EXT_SIMPLE_CONFIG(zicntr, ZICNTR);
{0}, KVM_ISA_EXT_SIMPLE_CONFIG(zicond, ZICOND);
}, KVM_ISA_EXT_SIMPLE_CONFIG(zicsr, ZICSR);
}; KVM_ISA_EXT_SIMPLE_CONFIG(zifencei, ZIFENCEI);
KVM_ISA_EXT_SIMPLE_CONFIG(zihintpause, ZIHINTPAUSE);
static struct vcpu_reg_list zihintpause_config = { KVM_ISA_EXT_SIMPLE_CONFIG(zihpm, ZIHPM);
.sublists = {
BASE_SUBLIST,
ZIHINTPAUSE_REGS_SUBLIST,
{0},
},
};
static struct vcpu_reg_list zba_config = {
.sublists = {
BASE_SUBLIST,
ZBA_REGS_SUBLIST,
{0},
},
};
static struct vcpu_reg_list zbb_config = {
.sublists = {
BASE_SUBLIST,
ZBB_REGS_SUBLIST,
{0},
},
};
static struct vcpu_reg_list zbs_config = {
.sublists = {
BASE_SUBLIST,
ZBS_REGS_SUBLIST,
{0},
},
};
static struct vcpu_reg_list zicntr_config = {
.sublists = {
BASE_SUBLIST,
ZICNTR_REGS_SUBLIST,
{0},
},
};
static struct vcpu_reg_list zicond_config = {
.sublists = {
BASE_SUBLIST,
ZICOND_REGS_SUBLIST,
{0},
},
};
static struct vcpu_reg_list zicsr_config = {
.sublists = {
BASE_SUBLIST,
ZICSR_REGS_SUBLIST,
{0},
},
};
static struct vcpu_reg_list zifencei_config = {
.sublists = {
BASE_SUBLIST,
ZIFENCEI_REGS_SUBLIST,
{0},
},
};
static struct vcpu_reg_list zihpm_config = {
.sublists = {
BASE_SUBLIST,
ZIHPM_REGS_SUBLIST,
{0},
},
};
static struct vcpu_reg_list aia_config = {
.sublists = {
BASE_SUBLIST,
AIA_REGS_SUBLIST,
{0},
},
};
static struct vcpu_reg_list smstateen_config = {
.sublists = {
BASE_SUBLIST,
SMSTATEEN_REGS_SUBLIST,
{0},
},
};
static struct vcpu_reg_list fp_f_config = {
.sublists = {
BASE_SUBLIST,
FP_F_REGS_SUBLIST,
{0},
},
};
static struct vcpu_reg_list fp_d_config = {
.sublists = {
BASE_SUBLIST,
FP_D_REGS_SUBLIST,
{0},
},
};
struct vcpu_reg_list *vcpu_configs[] = { struct vcpu_reg_list *vcpu_configs[] = {
&h_config, &config_aia,
&zicbom_config, &config_fp_f,
&zicboz_config, &config_fp_d,
&svpbmt_config, &config_h,
&sstc_config, &config_smstateen,
&svinval_config, &config_sstc,
&zihintpause_config, &config_svinval,
&zba_config, &config_svnapot,
&zbb_config, &config_svpbmt,
&zbs_config, &config_zba,
&zicntr_config, &config_zbb,
&zicond_config, &config_zbs,
&zicsr_config, &config_zicbom,
&zifencei_config, &config_zicboz,
&zihpm_config, &config_zicntr,
&aia_config, &config_zicond,
&smstateen_config, &config_zicsr,
&fp_f_config, &config_zifencei,
&fp_d_config, &config_zihintpause,
&config_zihpm,
}; };
int vcpu_configs_n = ARRAY_SIZE(vcpu_configs); int vcpu_configs_n = ARRAY_SIZE(vcpu_configs);
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