Commit c19a5f32 authored by Tao Zhou's avatar Tao Zhou Committed by Alex Deucher

drm/amdgpu: export umc error address convert interface

Make it global so we can convert specific mca address.

v2: rename query_error_address_per_channel to
convert_ras_error_address
Signed-off-by: default avatarTao Zhou <tao.zhou1@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent baf28cc1
...@@ -22,6 +22,8 @@ ...@@ -22,6 +22,8 @@
#define __AMDGPU_UMC_H__ #define __AMDGPU_UMC_H__
#include "amdgpu_ras.h" #include "amdgpu_ras.h"
#define UMC_INVALID_ADDR 0x1ULL
/* /*
* (addr / 256) * 4096, the higher 26 bits in ErrorAddr * (addr / 256) * 4096, the higher 26 bits in ErrorAddr
* is the index of 4KB block * is the index of 4KB block
...@@ -51,6 +53,10 @@ struct amdgpu_umc_ras { ...@@ -51,6 +53,10 @@ struct amdgpu_umc_ras {
struct amdgpu_ras_block_object ras_block; struct amdgpu_ras_block_object ras_block;
void (*err_cnt_init)(struct amdgpu_device *adev); void (*err_cnt_init)(struct amdgpu_device *adev);
bool (*query_ras_poison_mode)(struct amdgpu_device *adev); bool (*query_ras_poison_mode)(struct amdgpu_device *adev);
void (*convert_ras_error_address)(struct amdgpu_device *adev,
struct ras_err_data *err_data,
uint32_t umc_reg_offset, uint32_t ch_inst,
uint32_t umc_inst, uint64_t mca_addr);
void (*ecc_info_query_ras_error_count)(struct amdgpu_device *adev, void (*ecc_info_query_ras_error_count)(struct amdgpu_device *adev,
void *ras_error_status); void *ras_error_status);
void (*ecc_info_query_ras_error_address)(struct amdgpu_device *adev, void (*ecc_info_query_ras_error_address)(struct amdgpu_device *adev,
......
...@@ -452,9 +452,8 @@ static void umc_v6_7_query_ras_error_count(struct amdgpu_device *adev, ...@@ -452,9 +452,8 @@ static void umc_v6_7_query_ras_error_count(struct amdgpu_device *adev,
static void umc_v6_7_query_error_address(struct amdgpu_device *adev, static void umc_v6_7_query_error_address(struct amdgpu_device *adev,
struct ras_err_data *err_data, struct ras_err_data *err_data,
uint32_t umc_reg_offset, uint32_t umc_reg_offset, uint32_t ch_inst,
uint32_t ch_inst, uint32_t umc_inst, uint64_t mca_addr)
uint32_t umc_inst)
{ {
uint32_t mc_umc_status_addr; uint32_t mc_umc_status_addr;
uint32_t channel_index; uint32_t channel_index;
...@@ -540,9 +539,8 @@ static void umc_v6_7_query_ras_error_address(struct amdgpu_device *adev, ...@@ -540,9 +539,8 @@ static void umc_v6_7_query_ras_error_address(struct amdgpu_device *adev,
ch_inst); ch_inst);
umc_v6_7_query_error_address(adev, umc_v6_7_query_error_address(adev,
err_data, err_data,
umc_reg_offset, umc_reg_offset, ch_inst,
ch_inst, umc_inst, UMC_INVALID_ADDR);
umc_inst);
} }
} }
...@@ -583,4 +581,5 @@ struct amdgpu_umc_ras umc_v6_7_ras = { ...@@ -583,4 +581,5 @@ struct amdgpu_umc_ras umc_v6_7_ras = {
.query_ras_poison_mode = umc_v6_7_query_ras_poison_mode, .query_ras_poison_mode = umc_v6_7_query_ras_poison_mode,
.ecc_info_query_ras_error_count = umc_v6_7_ecc_info_query_ras_error_count, .ecc_info_query_ras_error_count = umc_v6_7_ecc_info_query_ras_error_count,
.ecc_info_query_ras_error_address = umc_v6_7_ecc_info_query_ras_error_address, .ecc_info_query_ras_error_address = umc_v6_7_ecc_info_query_ras_error_address,
.convert_ras_error_address = umc_v6_7_query_error_address,
}; };
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