Commit c2258a94 authored by Krzysztof Kozlowski's avatar Krzysztof Kozlowski Committed by Neil Armstrong

arm64: dts: amlogic: add missing cache properties

As all level 2 and level 3 caches are unified, add required
cache-unified properties to fix warnings like:

  meson-a1-ad401.dtb: l2-cache0: 'cache-unified' is a required property
Signed-off-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: default avatarMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Link: https://lore.kernel.org/r/20230421223211.115612-1-krzysztof.kozlowski@linaro.orgSigned-off-by: default avatarNeil Armstrong <neil.armstrong@linaro.org>
parent cb3f4e8c
......@@ -37,6 +37,7 @@ cpu1: cpu@1 {
l2: l2-cache0 {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};
......
......@@ -106,6 +106,7 @@ cpu3: cpu@3 {
l2: l2-cache0 {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};
......
......@@ -51,6 +51,7 @@ cpu3: cpu@3 {
l2: l2-cache0 {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};
......
......@@ -106,6 +106,7 @@ cpu103: cpu@103 {
l2: l2-cache0 {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};
};
......
......@@ -133,6 +133,7 @@ cpu3: cpu@3 {
l2: l2-cache0 {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};
......
......@@ -89,6 +89,7 @@ cpu3: cpu@3 {
l2: l2-cache0 {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment