Commit c32e176a authored by Arnd Bergmann's avatar Arnd Bergmann

Merge tag 'v4.14-rockchip-dts32-2' of...

Merge tag 'v4.14-rockchip-dts32-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt

Pull "second round of Rockchip dts32 changes for 4.14" from Heiko Stübner:

A lot of attention for the rv1108 soc targetted at media-processing
(usb, operating points, spi, pwm, adc, watchdog, i2c and devices for
its evb).

RK3228/3229 gets iommu and spi nodes. Similar to the rk3288 which
also gets some more iommu nodes as well as getting converted to 64
bit addresses due to wanting to address more than 4GB of memory
via LPAE.

* tag 'v4.14-rockchip-dts32-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  ARM: dts: rockchip: enable usb for rv1108-evb
  ARM: dts: rockchip: add usb nodes for rv1108 SoCs
  dt-bindings: update grf-binding for rv1108 SoCs
  ARM: dts: rockchip: add cpu power supply for rv1108 evb
  ARM: dts: rockchip: add cpu opp table for rv1108
  ARM: dts: rockchip: add rk322x iommu nodes
  ARM: dts: rockchip: add accelerometer bma250e dt node for rv1108 evb
  ARM: dts: rockchip: add pmic rk805 dt node for rv1108 evb
  ARM: dts: rockchip: add pwm backlight for rv1108 evb
  ARM: dts: rockchip: add pwm dt nodes for rv1108
  ARM: dts: rockchip: add spi dt node for rv1108
  ARM: dts: rockchip: add saradc support for rv1108
  ARM: dts: rockchip: add watchdog dt node for rv1108
  ARM: dts: rockchip: add i2c dt nodes for rv1108
  clk: rockchip: fix up indentation of some RV1108 clock-ids
  clk: rockchip: rename the clk id for HCLK_I2S1_2CH
  clk: rockchip: add more clk ids for rv1108
  ARM: dts: rockchip: add more iommu nodes on rk3288
  ARM: dts: rockchip: convert rk3288 device tree files to 64 bits
  ARM: dts: rockchip: add spi node and spi pinctrl on rk3228/rk3229
Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 7bf53b96 274ff50d
......@@ -21,6 +21,7 @@ Required Properties:
- "rockchip,rk3328-grf", "syscon": for rk3328
- "rockchip,rk3368-grf", "syscon": for rk3368
- "rockchip,rk3399-grf", "syscon": for rk3399
- "rockchip,rv1108-grf", "syscon": for rv1108
- compatible: PMUGRF should be one of the following:
- "rockchip,rk3368-pmugrf", "syscon": for rk3368
- "rockchip,rk3399-pmugrf", "syscon": for rk3399
......@@ -28,6 +29,8 @@ Required Properties:
- "rockchip,rk3288-sgrf", "syscon": for rk3288
- compatible: USB2PHYGRF should be one of the followings
- "rockchip,rk3328-usb2phy-grf", "syscon": for rk3328
- compatible: USBGRF should be one of the following
- "rockchip,rv1108-usbgrf", "syscon": for rv1108
- reg: physical base address of the controller and length of memory mapped
region.
......
......@@ -55,6 +55,7 @@ aliases {
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
spi0 = &spi0;
};
cpus {
......@@ -405,6 +406,19 @@ i2c3: i2c@11080000 {
status = "disabled";
};
spi0: spi@11090000 {
compatible = "rockchip,rk3228-spi";
reg = <0x11090000 0x1000>;
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
clock-names = "spiclk", "apb_pclk";
pinctrl-names = "default";
pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0 &spi0_cs1>;
status = "disabled";
};
wdt: watchdog@110a0000 {
compatible = "snps,dw-wdt";
reg = <0x110a0000 0x100>;
......@@ -544,6 +558,42 @@ tsadc: tsadc@11150000 {
status = "disabled";
};
vpu_mmu: iommu@20020800 {
compatible = "rockchip,iommu";
reg = <0x20020800 0x100>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "vpu_mmu";
iommu-cells = <0>;
status = "disabled";
};
vdec_mmu: iommu@20030480 {
compatible = "rockchip,iommu";
reg = <0x20030480 0x40>, <0x200304c0 0x40>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "vdec_mmu";
iommu-cells = <0>;
status = "disabled";
};
vop_mmu: iommu@20053f00 {
compatible = "rockchip,iommu";
reg = <0x20053f00 0x100>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "vop_mmu";
iommu-cells = <0>;
status = "disabled";
};
iep_mmu: iommu@20070800 {
compatible = "rockchip,iommu";
reg = <0x20070800 0x100>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "iep_mmu";
iommu-cells = <0>;
status = "disabled";
};
sdmmc: dwmmc@30000000 {
compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x30000000 0x4000>;
......@@ -900,6 +950,42 @@ i2c3_xfer: i2c3-xfer {
};
};
spi-0 {
spi0_clk: spi0-clk {
rockchip,pins = <0 9 RK_FUNC_2 &pcfg_pull_up>;
};
spi0_cs0: spi0-cs0 {
rockchip,pins = <0 14 RK_FUNC_2 &pcfg_pull_up>;
};
spi0_tx: spi0-tx {
rockchip,pins = <0 11 RK_FUNC_2 &pcfg_pull_up>;
};
spi0_rx: spi0-rx {
rockchip,pins = <0 13 RK_FUNC_2 &pcfg_pull_up>;
};
spi0_cs1: spi0-cs1 {
rockchip,pins = <1 12 RK_FUNC_1 &pcfg_pull_up>;
};
};
spi-1 {
spi1_clk: spi1-clk {
rockchip,pins = <0 23 RK_FUNC_2 &pcfg_pull_up>;
};
spi1_cs0: spi1-cs0 {
rockchip,pins = <2 2 RK_FUNC_2 &pcfg_pull_up>;
};
spi1_rx: spi1-rx {
rockchip,pins = <2 0 RK_FUNC_2 &pcfg_pull_up>;
};
spi1_tx: spi1-tx {
rockchip,pins = <2 1 RK_FUNC_2 &pcfg_pull_up>;
};
spi1_cs1: spi1-cs1 {
rockchip,pins = <2 3 RK_FUNC_2 &pcfg_pull_up>;
};
};
i2s1 {
i2s1_bus: i2s1-bus {
rockchip,pins = <0 8 RK_FUNC_1 &pcfg_pull_none>,
......
......@@ -45,7 +45,7 @@
/ {
memory@0 {
device_type = "memory";
reg = <0x0 0x80000000>;
reg = <0x0 0x0 0x0 0x80000000>;
};
adc-keys {
......
......@@ -47,7 +47,7 @@ / {
compatible = "rockchip,rk3288-fennec", "rockchip,rk3288";
memory@0 {
reg = <0x0 0x80000000>;
reg = <0x0 0x0 0x0 0x80000000>;
device_type = "memory";
};
......
......@@ -47,7 +47,7 @@
/ {
memory@0 {
device_type = "memory";
reg = <0 0x80000000>;
reg = <0x0 0x0 0x0 0x80000000>;
};
ext_gmac: external-gmac-clock {
......
......@@ -46,7 +46,7 @@
/ {
memory@0 {
device_type = "memory";
reg = <0 0x80000000>;
reg = <0x0 0x0 0x0 0x80000000>;
};
adc-keys {
......
......@@ -54,7 +54,7 @@ chosen {
memory@0 {
device_type = "memory";
reg = <0 0x80000000>;
reg = <0x0 0x0 0x0 0x80000000>;
};
ext_gmac: external-gmac-clock {
......
......@@ -55,7 +55,7 @@ / {
*/
memory {
device_type = "memory";
reg = <0 0x8000000>;
reg = <0x0 0x0 0x0 0x8000000>;
};
aliases {
......
......@@ -50,7 +50,7 @@ / {
memory@0 {
device_type = "memory";
reg = <0 0x80000000>;
reg = <0x0 0x0 0x0 0x80000000>;
};
ext_gmac: external-gmac-clock {
......
......@@ -50,7 +50,7 @@ / {
memory@0 {
device_type = "memory";
reg = <0x0 0x80000000>;
reg = <0x0 0x0 0x0 0x80000000>;
};
ext_gmac: external-gmac-clock {
......
......@@ -43,7 +43,7 @@
/ {
memory@0 {
reg = <0x0 0x80000000>;
reg = <0x0 0x0 0x0 0x80000000>;
device_type = "memory";
};
......
......@@ -50,7 +50,7 @@ / {
compatible = "asus,rk3288-tinker", "rockchip,rk3288";
memory {
reg = <0x0 0x80000000>;
reg = <0x0 0x0 0x0 0x80000000>;
device_type = "memory";
};
......
......@@ -49,7 +49,7 @@
/ {
memory@0 {
device_type = "memory";
reg = <0x0 0x80000000>;
reg = <0x0 0x0 0x0 0x80000000>;
};
gpio_keys: gpio-keys {
......
This diff is collapsed.
......@@ -54,12 +54,186 @@ memory@60000000 {
chosen {
stdout-path = "serial2:1500000n8";
};
backlight: backlight {
compatible = "pwm-backlight";
brightness-levels = <
0 1 2 3 4 5 6 7
8 9 10 11 12 13 14 15
16 17 18 19 20 21 22 23
24 25 26 27 28 29 30 31
32 33 34 35 36 37 38 39
40 41 42 43 44 45 46 47
48 49 50 51 52 53 54 55
56 57 58 59 60 61 62 63
64 65 66 67 68 69 70 71
72 73 74 75 76 77 78 79
80 81 82 83 84 85 86 87
88 89 90 91 92 93 94 95
96 97 98 99 100 101 102 103
104 105 106 107 108 109 110 111
112 113 114 115 116 117 118 119
120 121 122 123 124 125 126 127
128 129 130 131 132 133 134 135
136 137 138 139 140 141 142 143
144 145 146 147 148 149 150 151
152 153 154 155 156 157 158 159
160 161 162 163 164 165 166 167
168 169 170 171 172 173 174 175
176 177 178 179 180 181 182 183
184 185 186 187 188 189 190 191
192 193 194 195 196 197 198 199
200 201 202 203 204 205 206 207
208 209 210 211 212 213 214 215
216 217 218 219 220 221 222 223
224 225 226 227 228 229 230 231
232 233 234 235 236 237 238 239
240 241 242 243 244 245 246 247
248 249 250 251 252 253 254 255>;
default-brightness-level = <200>;
pwms = <&pwm0 0 25000 0>;
};
vcc_sys: vsys-regulator {
compatible = "regulator-fixed";
regulator-name = "vsys";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-boot-on;
};
};
&cpu0 {
cpu-supply = <&vdd_core>;
};
&i2c0 {
status = "okay";
i2c-scl-rising-time-ns = <275>;
i2c-scl-falling-time-ns = <16>;
clock-frequency = <400000>;
rk805: pmic@18 {
compatible = "rockchip,rk805";
reg = <0x18>;
interrupt-parent = <&gpio0>;
interrupts = <RK_PB4 IRQ_TYPE_LEVEL_LOW>;
rockchip,system-power-controller;
vcc1-supply = <&vcc_sys>;
vcc2-supply = <&vcc_sys>;
vcc3-supply = <&vcc_sys>;
vcc4-supply = <&vcc_sys>;
vcc5-supply = <&vcc_sys>;
vcc6-supply = <&vcc_sys>;
regulators {
vdd_core: DCDC_REG1 {
regulator-name= "vdd_core";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1500000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-state-enabled;
regulator-state-uv = <900000>;
};
};
vdd_cam: DCDC_REG2 {
regulator-name= "vdd_cam";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <2000000>;
regulator-state-mem {
regulator-state-disabled;
};
};
vcc_ddr: DCDC_REG3 {
regulator-name= "vcc_ddr";
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-state-enabled;
};
};
vcc_io: DCDC_REG4 {
regulator-name= "vcc_io";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-state-enabled;
regulator-state-uv = <3300000>;
};
};
vdd_10: LDO_REG1 {
regulator-name= "vdd_10";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-state-disabled;
};
};
vcc_18: LDO_REG2 {
regulator-name= "vcc_18";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-state-disabled;
};
};
vdd10_pmu: LDO_REG3 {
regulator-name= "vdd10_pmu";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-state-enabled;
regulator-state-uv = <1000000>;
};
};
};
};
bma250: accelerometer@19 {
compatible = "bosch,bma250e";
reg = <0x19>;
interrupt-parent = <&gpio0>;
interrupts = <RK_PB3 IRQ_TYPE_LEVEL_LOW>;
};
};
&pwm0 {
status = "okay";
};
&sdmmc {
status = "okay";
};
&u2phy {
status = "okay";
u2phy_host: host-port {
status = "okay";
};
u2phy_otg: otg-port {
status = "okay";
};
};
&uart0 {
status = "okay";
};
......@@ -71,3 +245,15 @@ &uart1 {
&uart2 {
status = "okay";
};
&usb_host_ehci {
status = "okay";
};
&usb_host_ohci {
status = "okay";
};
&usb_otg {
status = "okay";
};
This diff is collapsed.
......@@ -43,12 +43,73 @@
#define SCLK_SDMMC_SAMPLE 84
#define SCLK_SDIO_SAMPLE 85
#define SCLK_EMMC_SAMPLE 86
#define SCLK_VENC_CORE 87
#define SCLK_HEVC_CORE 88
#define SCLK_HEVC_CABAC 89
#define SCLK_PWM0_PMU 90
#define SCLK_I2C0_PMU 91
#define SCLK_WIFI 92
#define SCLK_CIFOUT 93
#define SCLK_MIPI_CSI_OUT 94
#define SCLK_CIF0 95
#define SCLK_CIF1 96
#define SCLK_CIF2 97
#define SCLK_CIF3 98
#define SCLK_DSP 99
#define SCLK_DSP_IOP 100
#define SCLK_DSP_EPP 101
#define SCLK_DSP_EDP 102
#define SCLK_DSP_EDAP 103
#define SCLK_CVBS_HOST 104
#define SCLK_HDMI_SFR 105
#define SCLK_HDMI_CEC 106
#define SCLK_CRYPTO 107
#define SCLK_SPI 108
#define SCLK_SARADC 109
#define SCLK_TSADC 110
#define SCLK_MACPHY_PRE 111
#define SCLK_MACPHY 112
#define SCLK_MACPHY_RX 113
#define SCLK_MAC_REF 114
#define SCLK_MAC_REFOUT 115
#define SCLK_DSP_PFM 116
#define SCLK_RGA 117
#define SCLK_I2C1 118
#define SCLK_I2C2 119
#define SCLK_I2C3 120
#define SCLK_PWM 121
#define SCLK_ISP 122
#define SCLK_USBPHY 123
#define SCLK_I2S0_SRC 124
#define SCLK_I2S1_SRC 125
#define SCLK_I2S2_SRC 126
#define SCLK_UART0_SRC 127
#define SCLK_UART1_SRC 128
#define SCLK_UART2_SRC 129
#define DCLK_VOP_SRC 185
#define DCLK_HDMIPHY 186
#define DCLK_VOP 187
/* aclk gates */
#define ACLK_DMAC 192
#define ACLK_PRE 193
#define ACLK_CORE 194
#define ACLK_ENMCORE 195
#define ACLK_RKVENC 196
#define ACLK_RKVDEC 197
#define ACLK_VPU 198
#define ACLK_CIF0 199
#define ACLK_VIO0 200
#define ACLK_VIO1 201
#define ACLK_VOP 202
#define ACLK_IEP 203
#define ACLK_RGA 204
#define ACLK_ISP 205
#define ACLK_CIF1 206
#define ACLK_CIF2 207
#define ACLK_CIF3 208
#define ACLK_PERI 209
/* pclk gates */
#define PCLK_GPIO1 256
......@@ -67,10 +128,23 @@
#define PCLK_PWM 269
#define PCLK_TIMER 270
#define PCLK_PERI 271
#define PCLK_GPIO0_PMU 272
#define PCLK_I2C0_PMU 273
#define PCLK_PWM0_PMU 274
#define PCLK_ISP 275
#define PCLK_VIO 276
#define PCLK_MIPI_DSI 277
#define PCLK_HDMI_CTRL 278
#define PCLK_SARADC 279
#define PCLK_DSP_CFG 280
#define PCLK_BUS 281
#define PCLK_EFUSE0 282
#define PCLK_EFUSE1 283
#define PCLK_WDT 284
/* hclk gates */
#define HCLK_I2S0_8CH 320
#define HCLK_I2S1_8CH 321
#define HCLK_I2S1_2CH 321
#define HCLK_I2S2_2CH 322
#define HCLK_NANDC 323
#define HCLK_SDMMC 324
......@@ -78,20 +152,37 @@
#define HCLK_EMMC 326
#define HCLK_PERI 327
#define HCLK_SFC 328
#define HCLK_RKVENC 329
#define HCLK_RKVDEC 330
#define HCLK_CIF0 331
#define HCLK_VIO 332
#define HCLK_VOP 333
#define HCLK_IEP 334
#define HCLK_RGA 335
#define HCLK_ISP 336
#define HCLK_CRYPTO_MST 337
#define HCLK_CRYPTO_SLV 338
#define HCLK_HOST0 339
#define HCLK_OTG 340
#define HCLK_CIF1 341
#define HCLK_CIF2 342
#define HCLK_CIF3 343
#define HCLK_BUS 344
#define HCLK_VPU 345
#define CLK_NR_CLKS (HCLK_SFC + 1)
#define CLK_NR_CLKS (HCLK_VPU + 1)
/* reset id */
#define SRST_CORE_PO_AD 0
#define SRST_CORE_PO_AD 0
#define SRST_CORE_AD 1
#define SRST_L2_AD 2
#define SRST_CPU_NIU_AD 3
#define SRST_CPU_NIU_AD 3
#define SRST_CORE_PO 4
#define SRST_CORE 5
#define SRST_L2 6
#define SRST_L2 6
#define SRST_CORE_DBG 8
#define PRST_DBG 9
#define RST_DAP 10
#define RST_DAP 10
#define PRST_DBG_NIU 11
#define ARST_STRC_SYS_AD 15
......@@ -158,9 +249,9 @@
#define HRST_SYSBUS 75
#define PRST_USBGRF 76
#define ARST_PERIPH_NIU 80
#define HRST_PERIPH_NIU 81
#define PRST_PERIPH_NIU 82
#define ARST_PERIPH_NIU 80
#define HRST_PERIPH_NIU 81
#define PRST_PERIPH_NIU 82
#define HRST_PERIPH 83
#define HRST_SDMMC 84
#define HRST_SDIO 85
......@@ -178,7 +269,7 @@
#define HRST_HOST0_AUX 96
#define HRST_HOST0_ARB 97
#define SRST_HOST0_EHCIPHY 98
#define SRST_HOST0_UTMI 99
#define SRST_HOST0_UTMI 99
#define SRST_USBPOR 100
#define SRST_UTMI0 101
#define SRST_UTMI1 102
......@@ -225,21 +316,21 @@
#define HRST_VPU_NIU 141
#define ARST_VPU 142
#define HRST_VPU 143
#define ARST_RKVDEC_NIU 144
#define HRST_RKVDEC_NIU 145
#define ARST_RKVDEC_NIU 144
#define HRST_RKVDEC_NIU 145
#define ARST_RKVDEC 146
#define HRST_RKVDEC 147
#define SRST_RKVDEC_CABAC 148
#define SRST_RKVDEC_CORE 149
#define ARST_RKVENC_NIU 150
#define HRST_RKVENC_NIU 151
#define ARST_RKVENC_NIU 150
#define HRST_RKVENC_NIU 151
#define ARST_RKVENC 152
#define HRST_RKVENC 153
#define SRST_RKVENC_CORE 154
#define SRST_DSP_CORE 156
#define SRST_DSP_SYS 157
#define SRST_DSP_GLOBAL 158
#define SRST_DSP_GLOBAL 158
#define SRST_DSP_OECM 159
#define PRST_DSP_IOP_NIU 160
#define ARST_DSP_EPP_NIU 161
......@@ -257,7 +348,7 @@
#define SRST_PMU_I2C0 173
#define PRST_PMU_I2C0 174
#define PRST_PMU_GPIO0 175
#define PRST_PMU_INTMEM 176
#define PRST_PMU_INTMEM 176
#define PRST_PMU_PWM0 177
#define SRST_PMU_PWM0 178
#define PRST_PMU_GRF 179
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment