Commit c3eea194 authored by Thor Thayer's avatar Thor Thayer Committed by Borislav Petkov

EDAC, altera: Add Altera L2 cache and OCRAM support

Add L2 Cache and On-Chip RAM EDAC support for the Altera SoCs. The SDRAM
controller is using the Memory Controller model.

Each type of ECC is individually configurable.
Signed-off-by: default avatarThor Thayer <tthayer@opensource.altera.com>
Cc: devicetree@vger.kernel.org
Cc: dinguyen@opensource.altera.com
Cc: galak@codeaurora.org
Cc: grant.likely@linaro.org
Cc: ijc+devicetree@hellion.org.uk
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux@arm.linux.org.uk
Cc: linux-doc@vger.kernel.org
Cc: linux-edac <linux-edac@vger.kernel.org>
Cc: mark.rutland@arm.com
Cc: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
Cc: pawel.moll@arm.com
Cc: robh+dt@kernel.org
Link: http://lkml.kernel.org/r/1455132384-17108-1-git-send-email-tthayer@opensource.altera.comSigned-off-by: default avatarBorislav Petkov <bp@suse.de>
parent 9bf4f005
...@@ -367,14 +367,30 @@ config EDAC_OCTEON_PCI ...@@ -367,14 +367,30 @@ config EDAC_OCTEON_PCI
Support for error detection and correction on the Support for error detection and correction on the
Cavium Octeon family of SOCs. Cavium Octeon family of SOCs.
config EDAC_ALTERA_MC config EDAC_ALTERA
bool "Altera SDRAM Memory Controller EDAC" bool "Altera SOCFPGA ECC"
depends on EDAC_MM_EDAC=y && ARCH_SOCFPGA depends on EDAC_MM_EDAC=y && ARCH_SOCFPGA
help help
Support for error detection and correction on the Support for error detection and correction on the
Altera SDRAM memory controller. Note that the Altera SOCs. This must be selected for SDRAM ECC.
preloader must initialize the SDRAM before loading Note that the preloader must initialize the SDRAM
the kernel. before loading the kernel.
config EDAC_ALTERA_L2C
bool "Altera L2 Cache ECC"
depends on EDAC_ALTERA=y
select CACHE_L2X0
help
Support for error detection and correction on the
Altera L2 cache Memory for Altera SoCs. This option
requires L2 cache so it will force that selection.
config EDAC_ALTERA_OCRAM
bool "Altera On-Chip RAM ECC"
depends on EDAC_ALTERA=y && SRAM && GENERIC_ALLOCATOR
help
Support for error detection and correction on the
Altera On-Chip RAM Memory for Altera SoCs.
config EDAC_SYNOPSYS config EDAC_SYNOPSYS
tristate "Synopsys DDR Memory Controller" tristate "Synopsys DDR Memory Controller"
......
...@@ -67,6 +67,6 @@ obj-$(CONFIG_EDAC_OCTEON_L2C) += octeon_edac-l2c.o ...@@ -67,6 +67,6 @@ obj-$(CONFIG_EDAC_OCTEON_L2C) += octeon_edac-l2c.o
obj-$(CONFIG_EDAC_OCTEON_LMC) += octeon_edac-lmc.o obj-$(CONFIG_EDAC_OCTEON_LMC) += octeon_edac-lmc.o
obj-$(CONFIG_EDAC_OCTEON_PCI) += octeon_edac-pci.o obj-$(CONFIG_EDAC_OCTEON_PCI) += octeon_edac-pci.o
obj-$(CONFIG_EDAC_ALTERA_MC) += altera_edac.o obj-$(CONFIG_EDAC_ALTERA) += altera_edac.o
obj-$(CONFIG_EDAC_SYNOPSYS) += synopsys_edac.o obj-$(CONFIG_EDAC_SYNOPSYS) += synopsys_edac.o
obj-$(CONFIG_EDAC_XGENE) += xgene_edac.o obj-$(CONFIG_EDAC_XGENE) += xgene_edac.o
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