drm/nouveau/pci/nv46: attempt to fix msi, and re-enable by default

Was not able to obtain a trace of NVRM due to kernel version annoyances,
however, experimentally confirmed that the WAR we use on NV50/G8x boards
works here too.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drivers/gpu/drm/nouveau/include/nvkm/subdev/pci.h

@@ -28,8 +28,8 @@ void nvkm_pci_rom_shadow(struct nvkm_pci *, bool shadow);
 
 int nv04_pci_new(struct nvkm_device *, int, struct nvkm_pci **);
 int nv40_pci_new(struct nvkm_device *, int, struct nvkm_pci **);
+int nv46_pci_new(struct nvkm_device *, int, struct nvkm_pci **);
 int nv4c_pci_new(struct nvkm_device *, int, struct nvkm_pci **);
-int nv50_pci_new(struct nvkm_device *, int, struct nvkm_pci **);
 int g84_pci_new(struct nvkm_device *, int, struct nvkm_pci **);
 int g94_pci_new(struct nvkm_device *, int, struct nvkm_pci **);
 int gf100_pci_new(struct nvkm_device *, int, struct nvkm_pci **);

drivers/gpu/drm/nouveau/nvkm/engine/device/base.c

@@ -637,7 +637,7 @@ nv46_chipset = {
 	.imem = nv40_instmem_new,
 	.mc = nv44_mc_new,
 	.mmu = nv44_mmu_new,
-	.pci = nv4c_pci_new,
+	.pci = nv46_pci_new,
 	.therm = nv40_therm_new,
 	.timer = nv41_timer_new,
 	.volt = nv40_volt_new,
@@ -822,7 +822,7 @@ nv50_chipset = {
 	.mc = nv50_mc_new,
 	.mmu = nv50_mmu_new,
 	.mxm = nv50_mxm_new,
-	.pci = nv50_pci_new,
+	.pci = nv46_pci_new,
 	.therm = nv50_therm_new,
 	.timer = nv41_timer_new,
 	.volt = nv40_volt_new,

drivers/gpu/drm/nouveau/nvkm/subdev/pci/Kbuild

@@ -2,8 +2,8 @@ nvkm-y += nvkm/subdev/pci/agp.o
 nvkm-y += nvkm/subdev/pci/base.o
 nvkm-y += nvkm/subdev/pci/nv04.o
 nvkm-y += nvkm/subdev/pci/nv40.o
+nvkm-y += nvkm/subdev/pci/nv46.o
 nvkm-y += nvkm/subdev/pci/nv4c.o
-nvkm-y += nvkm/subdev/pci/nv50.o
 nvkm-y += nvkm/subdev/pci/g84.o
 nvkm-y += nvkm/subdev/pci/g94.o
 nvkm-y += nvkm/subdev/pci/gf100.o

drivers/gpu/drm/nouveau/nvkm/subdev/pci/g84.c

@@ -30,7 +30,7 @@ g84_pci_func = {
 	.rd32 = nv40_pci_rd32,
 	.wr08 = nv40_pci_wr08,
 	.wr32 = nv40_pci_wr32,
-	.msi_rearm = nv50_pci_msi_rearm,
+	.msi_rearm = nv46_pci_msi_rearm,
 };
 
 int

drivers/gpu/drm/nouveau/nvkm/subdev/pci/nv50.c → drivers/gpu/drm/nouveau/nvkm/subdev/pci/nv46.c

@@ -25,11 +25,11 @@
 
 #include <core/pci.h>
 
-/* MSI re-arm through the PRI appears to be broken on NV50/G84/G86/G92,
+/* MSI re-arm through the PRI appears to be broken on NV46/NV50/G84/G86/G92,
  * so we access it via alternate PCI config space mechanisms.
  */
 void
-nv50_pci_msi_rearm(struct nvkm_pci *pci)
+nv46_pci_msi_rearm(struct nvkm_pci *pci)
 {
 	struct nvkm_device *device = pci->subdev.device;
 	struct pci_dev *pdev = device->func->pci(device)->pdev;
@@ -37,15 +37,15 @@ nv50_pci_msi_rearm(struct nvkm_pci *pci)
 }
 
 static const struct nvkm_pci_func
-nv50_pci_func = {
+nv46_pci_func = {
 	.rd32 = nv40_pci_rd32,
 	.wr08 = nv40_pci_wr08,
 	.wr32 = nv40_pci_wr32,
-	.msi_rearm = nv50_pci_msi_rearm,
+	.msi_rearm = nv46_pci_msi_rearm,
 };
 
 int
-nv50_pci_new(struct nvkm_device *device, int index, struct nvkm_pci **ppci)
+nv46_pci_new(struct nvkm_device *device, int index, struct nvkm_pci **ppci)
 {
-	return nvkm_pci_new_(&nv50_pci_func, device, index, ppci);
+	return nvkm_pci_new_(&nv46_pci_func, device, index, ppci);
 }

drivers/gpu/drm/nouveau/nvkm/subdev/pci/priv.h

@@ -18,5 +18,5 @@ void nv40_pci_wr08(struct nvkm_pci *, u16, u8);
 void nv40_pci_wr32(struct nvkm_pci *, u16, u32);
 void nv40_pci_msi_rearm(struct nvkm_pci *);
 
-void nv50_pci_msi_rearm(struct nvkm_pci *);
+void nv46_pci_msi_rearm(struct nvkm_pci *);
 #endif