Commit c503d8ae authored by Amit Cohen's avatar Amit Cohen Committed by Jakub Kicinski

mlxsw: spectrum: Add a copy of 'struct mlxsw_config_profile' for Spectrum-4

Starting from Spectrum-4, the maximum number of LAG IDs can be configured
by software via CONFIG_PROFILE command during driver initialization.

Add a dedicated instance of 'struct mlxsw_config_profile' for Spectrum-4
and set the 'max_lag' field to 128, which is the same amount of LAG entries
as in Spectrum-{2,3}. Without this configuration, firmware reserves 256
(the value of 'cap_max_lag' resource) entries at beginning of PGT table for
LAG identifiers, which means that less entries in PGT will be available.
Signed-off-by: default avatarAmit Cohen <amcohen@nvidia.com>
Reviewed-by: default avatarIdo Schimmel <idosch@nvidia.com>
Reviewed-by: default avatarPetr Machata <petrm@nvidia.com>
Signed-off-by: default avatarPetr Machata <petrm@nvidia.com>
Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parent cf735d4c
...@@ -3512,6 +3512,33 @@ static const struct mlxsw_config_profile mlxsw_sp2_config_profile = { ...@@ -3512,6 +3512,33 @@ static const struct mlxsw_config_profile mlxsw_sp2_config_profile = {
.cqe_time_stamp_type = MLXSW_CMD_MBOX_CONFIG_PROFILE_CQE_TIME_STAMP_TYPE_UTC, .cqe_time_stamp_type = MLXSW_CMD_MBOX_CONFIG_PROFILE_CQE_TIME_STAMP_TYPE_UTC,
}; };
/* Reduce number of LAGs from full capacity (256) to the maximum supported LAGs
* in Spectrum-2/3, to avoid regression in number of free entries in the PGT
* table.
*/
#define MLXSW_SP4_CONFIG_PROFILE_MAX_LAG 128
static const struct mlxsw_config_profile mlxsw_sp4_config_profile = {
.used_max_lag = 1,
.max_lag = MLXSW_SP4_CONFIG_PROFILE_MAX_LAG,
.used_flood_mode = 1,
.flood_mode = MLXSW_CMD_MBOX_CONFIG_PROFILE_FLOOD_MODE_CONTROLLED,
.used_max_ib_mc = 1,
.max_ib_mc = 0,
.used_max_pkey = 1,
.max_pkey = 0,
.used_ubridge = 1,
.ubridge = 1,
.swid_config = {
{
.used_type = 1,
.type = MLXSW_PORT_SWID_TYPE_ETH,
}
},
.used_cqe_time_stamp_type = 1,
.cqe_time_stamp_type = MLXSW_CMD_MBOX_CONFIG_PROFILE_CQE_TIME_STAMP_TYPE_UTC,
};
static void static void
mlxsw_sp_resource_size_params_prepare(struct mlxsw_core *mlxsw_core, mlxsw_sp_resource_size_params_prepare(struct mlxsw_core *mlxsw_core,
struct devlink_resource_size_params *kvd_size_params, struct devlink_resource_size_params *kvd_size_params,
...@@ -4042,7 +4069,7 @@ static struct mlxsw_driver mlxsw_sp4_driver = { ...@@ -4042,7 +4069,7 @@ static struct mlxsw_driver mlxsw_sp4_driver = {
.params_unregister = mlxsw_sp2_params_unregister, .params_unregister = mlxsw_sp2_params_unregister,
.ptp_transmitted = mlxsw_sp_ptp_transmitted, .ptp_transmitted = mlxsw_sp_ptp_transmitted,
.txhdr_len = MLXSW_TXHDR_LEN, .txhdr_len = MLXSW_TXHDR_LEN,
.profile = &mlxsw_sp2_config_profile, .profile = &mlxsw_sp4_config_profile,
.sdq_supports_cqe_v2 = true, .sdq_supports_cqe_v2 = true,
}; };
......
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