Commit c59224d1 authored by Linus Torvalds's avatar Linus Torvalds

Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux

Pull drm fixes from Dave Airlie:
 "Not a huge amount happening, some MAINTAINERS updates, radeon, vmwgfx
  and tegra fixes"

* 'drm-fixes' of git://people.freedesktop.org/~airlied/linux:
  drm/vmwgfx: avoid null pointer dereference at failure paths
  drm/vmwgfx: Make sure backing mobs are cleared when allocated. Update driver date.
  drm/vmwgfx: Remove some unused surface formats
  drm/radeon: enable speaker allocation setup on dce3.2
  drm/radeon: change audio enable logic
  drm/radeon: fix audio disable on dce6+
  drm/radeon: free uvd ring on unload
  drm/radeon: disable pll sharing for DP on DCE4.1
  drm/radeon: fix missing bo reservation
  drm/radeon: print the supported atpx function mask
  MAINTAINERS: update drm git tree entry
  MAINTAINERS: add entry for drm radeon driver
  drm/tegra: Add guard to avoid double disable/enable of RGB outputs
  gpu: host1x: do not check previously handled gathers
  drm/tegra: fix typo 'CONFIG_TEGRA_DRM_FBDEV'
parents a53c8ceb d668ca1c
...@@ -2848,12 +2848,22 @@ F: lib/kobj* ...@@ -2848,12 +2848,22 @@ F: lib/kobj*
DRM DRIVERS DRM DRIVERS
M: David Airlie <airlied@linux.ie> M: David Airlie <airlied@linux.ie>
L: dri-devel@lists.freedesktop.org L: dri-devel@lists.freedesktop.org
T: git git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6.git T: git git://people.freedesktop.org/~airlied/linux
S: Maintained S: Maintained
F: drivers/gpu/drm/ F: drivers/gpu/drm/
F: include/drm/ F: include/drm/
F: include/uapi/drm/ F: include/uapi/drm/
RADEON DRM DRIVERS
M: Alex Deucher <alexander.deucher@amd.com>
M: Christian König <christian.koenig@amd.com>
L: dri-devel@lists.freedesktop.org
T: git git://people.freedesktop.org/~agd5f/linux
S: Supported
F: drivers/gpu/drm/radeon/
F: include/drm/radeon*
F: include/uapi/drm/radeon*
INTEL DRM DRIVERS (excluding Poulsbo, Moorestown and derivative chipsets) INTEL DRM DRIVERS (excluding Poulsbo, Moorestown and derivative chipsets)
M: Daniel Vetter <daniel.vetter@ffwll.ch> M: Daniel Vetter <daniel.vetter@ffwll.ch>
M: Jani Nikula <jani.nikula@linux.intel.com> M: Jani Nikula <jani.nikula@linux.intel.com>
......
...@@ -1774,6 +1774,20 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc) ...@@ -1774,6 +1774,20 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc)
return ATOM_PPLL1; return ATOM_PPLL1;
DRM_ERROR("unable to allocate a PPLL\n"); DRM_ERROR("unable to allocate a PPLL\n");
return ATOM_PPLL_INVALID; return ATOM_PPLL_INVALID;
} else if (ASIC_IS_DCE41(rdev)) {
/* Don't share PLLs on DCE4.1 chips */
if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {
if (rdev->clock.dp_extclk)
/* skip PPLL programming if using ext clock */
return ATOM_PPLL_INVALID;
}
pll_in_use = radeon_get_pll_use_mask(crtc);
if (!(pll_in_use & (1 << ATOM_PPLL1)))
return ATOM_PPLL1;
if (!(pll_in_use & (1 << ATOM_PPLL2)))
return ATOM_PPLL2;
DRM_ERROR("unable to allocate a PPLL\n");
return ATOM_PPLL_INVALID;
} else if (ASIC_IS_DCE4(rdev)) { } else if (ASIC_IS_DCE4(rdev)) {
/* in DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock, /* in DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock,
* depending on the asic: * depending on the asic:
...@@ -1801,7 +1815,7 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc) ...@@ -1801,7 +1815,7 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc)
if (pll != ATOM_PPLL_INVALID) if (pll != ATOM_PPLL_INVALID)
return pll; return pll;
} }
} else if (!ASIC_IS_DCE41(rdev)) { /* Don't share PLLs on DCE4.1 chips */ } else {
/* use the same PPLL for all monitors with the same clock */ /* use the same PPLL for all monitors with the same clock */
pll = radeon_get_shared_nondp_ppll(crtc); pll = radeon_get_shared_nondp_ppll(crtc);
if (pll != ATOM_PPLL_INVALID) if (pll != ATOM_PPLL_INVALID)
......
...@@ -278,13 +278,15 @@ static int dce6_audio_chipset_supported(struct radeon_device *rdev) ...@@ -278,13 +278,15 @@ static int dce6_audio_chipset_supported(struct radeon_device *rdev)
return !ASIC_IS_NODCE(rdev); return !ASIC_IS_NODCE(rdev);
} }
static void dce6_audio_enable(struct radeon_device *rdev, void dce6_audio_enable(struct radeon_device *rdev,
struct r600_audio_pin *pin, struct r600_audio_pin *pin,
bool enable) bool enable)
{ {
if (!pin)
return;
WREG32_ENDPOINT(pin->offset, AZ_F0_CODEC_PIN_CONTROL_HOTPLUG_CONTROL, WREG32_ENDPOINT(pin->offset, AZ_F0_CODEC_PIN_CONTROL_HOTPLUG_CONTROL,
AUDIO_ENABLED); enable ? AUDIO_ENABLED : 0);
DRM_INFO("%s audio %d support\n", enable ? "Enabling" : "Disabling", pin->id);
} }
static const u32 pin_offsets[7] = static const u32 pin_offsets[7] =
...@@ -323,7 +325,8 @@ int dce6_audio_init(struct radeon_device *rdev) ...@@ -323,7 +325,8 @@ int dce6_audio_init(struct radeon_device *rdev)
rdev->audio.pin[i].connected = false; rdev->audio.pin[i].connected = false;
rdev->audio.pin[i].offset = pin_offsets[i]; rdev->audio.pin[i].offset = pin_offsets[i];
rdev->audio.pin[i].id = i; rdev->audio.pin[i].id = i;
dce6_audio_enable(rdev, &rdev->audio.pin[i], true); /* disable audio. it will be set up later */
dce6_audio_enable(rdev, &rdev->audio.pin[i], false);
} }
return 0; return 0;
......
...@@ -5475,9 +5475,9 @@ void evergreen_fini(struct radeon_device *rdev) ...@@ -5475,9 +5475,9 @@ void evergreen_fini(struct radeon_device *rdev)
radeon_wb_fini(rdev); radeon_wb_fini(rdev);
radeon_ib_pool_fini(rdev); radeon_ib_pool_fini(rdev);
radeon_irq_kms_fini(rdev); radeon_irq_kms_fini(rdev);
evergreen_pcie_gart_fini(rdev);
uvd_v1_0_fini(rdev); uvd_v1_0_fini(rdev);
radeon_uvd_fini(rdev); radeon_uvd_fini(rdev);
evergreen_pcie_gart_fini(rdev);
r600_vram_scratch_fini(rdev); r600_vram_scratch_fini(rdev);
radeon_gem_fini(rdev); radeon_gem_fini(rdev);
radeon_fence_driver_fini(rdev); radeon_fence_driver_fini(rdev);
......
...@@ -306,6 +306,15 @@ void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode ...@@ -306,6 +306,15 @@ void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode
return; return;
offset = dig->afmt->offset; offset = dig->afmt->offset;
/* disable audio prior to setting up hw */
if (ASIC_IS_DCE6(rdev)) {
dig->afmt->pin = dce6_audio_get_pin(rdev);
dce6_audio_enable(rdev, dig->afmt->pin, false);
} else {
dig->afmt->pin = r600_audio_get_pin(rdev);
r600_audio_enable(rdev, dig->afmt->pin, false);
}
evergreen_audio_set_dto(encoder, mode->clock); evergreen_audio_set_dto(encoder, mode->clock);
WREG32(HDMI_VBI_PACKET_CONTROL + offset, WREG32(HDMI_VBI_PACKET_CONTROL + offset,
...@@ -409,12 +418,16 @@ void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode ...@@ -409,12 +418,16 @@ void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode
WREG32(AFMT_RAMP_CONTROL1 + offset, 0x007FFFFF); WREG32(AFMT_RAMP_CONTROL1 + offset, 0x007FFFFF);
WREG32(AFMT_RAMP_CONTROL2 + offset, 0x00000001); WREG32(AFMT_RAMP_CONTROL2 + offset, 0x00000001);
WREG32(AFMT_RAMP_CONTROL3 + offset, 0x00000001); WREG32(AFMT_RAMP_CONTROL3 + offset, 0x00000001);
/* enable audio after to setting up hw */
if (ASIC_IS_DCE6(rdev))
dce6_audio_enable(rdev, dig->afmt->pin, true);
else
r600_audio_enable(rdev, dig->afmt->pin, true);
} }
void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable) void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable)
{ {
struct drm_device *dev = encoder->dev;
struct radeon_device *rdev = dev->dev_private;
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
...@@ -427,15 +440,6 @@ void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable) ...@@ -427,15 +440,6 @@ void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable)
if (!enable && !dig->afmt->enabled) if (!enable && !dig->afmt->enabled)
return; return;
if (enable) {
if (ASIC_IS_DCE6(rdev))
dig->afmt->pin = dce6_audio_get_pin(rdev);
else
dig->afmt->pin = r600_audio_get_pin(rdev);
} else {
dig->afmt->pin = NULL;
}
dig->afmt->enabled = enable; dig->afmt->enabled = enable;
DRM_DEBUG("%sabling HDMI interface @ 0x%04X for encoder 0x%x\n", DRM_DEBUG("%sabling HDMI interface @ 0x%04X for encoder 0x%x\n",
......
...@@ -142,12 +142,15 @@ void r600_audio_update_hdmi(struct work_struct *work) ...@@ -142,12 +142,15 @@ void r600_audio_update_hdmi(struct work_struct *work)
} }
/* enable the audio stream */ /* enable the audio stream */
static void r600_audio_enable(struct radeon_device *rdev, void r600_audio_enable(struct radeon_device *rdev,
struct r600_audio_pin *pin, struct r600_audio_pin *pin,
bool enable) bool enable)
{ {
u32 value = 0; u32 value = 0;
if (!pin)
return;
if (ASIC_IS_DCE4(rdev)) { if (ASIC_IS_DCE4(rdev)) {
if (enable) { if (enable) {
value |= 0x81000000; /* Required to enable audio */ value |= 0x81000000; /* Required to enable audio */
...@@ -158,7 +161,6 @@ static void r600_audio_enable(struct radeon_device *rdev, ...@@ -158,7 +161,6 @@ static void r600_audio_enable(struct radeon_device *rdev,
WREG32_P(R600_AUDIO_ENABLE, WREG32_P(R600_AUDIO_ENABLE,
enable ? 0x81000000 : 0x0, ~0x81000000); enable ? 0x81000000 : 0x0, ~0x81000000);
} }
DRM_INFO("%s audio %d support\n", enable ? "Enabling" : "Disabling", pin->id);
} }
/* /*
...@@ -178,8 +180,8 @@ int r600_audio_init(struct radeon_device *rdev) ...@@ -178,8 +180,8 @@ int r600_audio_init(struct radeon_device *rdev)
rdev->audio.pin[0].status_bits = 0; rdev->audio.pin[0].status_bits = 0;
rdev->audio.pin[0].category_code = 0; rdev->audio.pin[0].category_code = 0;
rdev->audio.pin[0].id = 0; rdev->audio.pin[0].id = 0;
/* disable audio. it will be set up later */
r600_audio_enable(rdev, &rdev->audio.pin[0], true); r600_audio_enable(rdev, &rdev->audio.pin[0], false);
return 0; return 0;
} }
......
...@@ -329,9 +329,6 @@ static void dce3_2_afmt_write_speaker_allocation(struct drm_encoder *encoder) ...@@ -329,9 +329,6 @@ static void dce3_2_afmt_write_speaker_allocation(struct drm_encoder *encoder)
u8 *sadb; u8 *sadb;
int sad_count; int sad_count;
/* XXX: setting this register causes hangs on some asics */
return;
list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
if (connector->encoder == encoder) { if (connector->encoder == encoder) {
radeon_connector = to_radeon_connector(connector); radeon_connector = to_radeon_connector(connector);
...@@ -460,6 +457,10 @@ void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mod ...@@ -460,6 +457,10 @@ void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mod
return; return;
offset = dig->afmt->offset; offset = dig->afmt->offset;
/* disable audio prior to setting up hw */
dig->afmt->pin = r600_audio_get_pin(rdev);
r600_audio_enable(rdev, dig->afmt->pin, false);
r600_audio_set_dto(encoder, mode->clock); r600_audio_set_dto(encoder, mode->clock);
WREG32(HDMI0_VBI_PACKET_CONTROL + offset, WREG32(HDMI0_VBI_PACKET_CONTROL + offset,
...@@ -531,6 +532,9 @@ void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mod ...@@ -531,6 +532,9 @@ void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mod
WREG32(HDMI0_RAMP_CONTROL3 + offset, 0x00000001); WREG32(HDMI0_RAMP_CONTROL3 + offset, 0x00000001);
r600_hdmi_audio_workaround(encoder); r600_hdmi_audio_workaround(encoder);
/* enable audio after to setting up hw */
r600_audio_enable(rdev, dig->afmt->pin, true);
} }
/* /*
...@@ -651,11 +655,6 @@ void r600_hdmi_enable(struct drm_encoder *encoder, bool enable) ...@@ -651,11 +655,6 @@ void r600_hdmi_enable(struct drm_encoder *encoder, bool enable)
if (!enable && !dig->afmt->enabled) if (!enable && !dig->afmt->enabled)
return; return;
if (enable)
dig->afmt->pin = r600_audio_get_pin(rdev);
else
dig->afmt->pin = NULL;
/* Older chipsets require setting HDMI and routing manually */ /* Older chipsets require setting HDMI and routing manually */
if (!ASIC_IS_DCE3(rdev)) { if (!ASIC_IS_DCE3(rdev)) {
if (enable) if (enable)
......
...@@ -2747,6 +2747,12 @@ int radeon_vm_bo_rmv(struct radeon_device *rdev, ...@@ -2747,6 +2747,12 @@ int radeon_vm_bo_rmv(struct radeon_device *rdev,
void r600_audio_update_hdmi(struct work_struct *work); void r600_audio_update_hdmi(struct work_struct *work);
struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev); struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev);
struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev); struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev);
void r600_audio_enable(struct radeon_device *rdev,
struct r600_audio_pin *pin,
bool enable);
void dce6_audio_enable(struct radeon_device *rdev,
struct r600_audio_pin *pin,
bool enable);
/* /*
* R600 vram scratch functions * R600 vram scratch functions
......
...@@ -219,7 +219,8 @@ static int radeon_atpx_verify_interface(struct radeon_atpx *atpx) ...@@ -219,7 +219,8 @@ static int radeon_atpx_verify_interface(struct radeon_atpx *atpx)
memcpy(&output, info->buffer.pointer, size); memcpy(&output, info->buffer.pointer, size);
/* TODO: check version? */ /* TODO: check version? */
printk("ATPX version %u\n", output.version); printk("ATPX version %u, functions 0x%08x\n",
output.version, output.function_bits);
radeon_atpx_parse_functions(&atpx->functions, output.function_bits); radeon_atpx_parse_functions(&atpx->functions, output.function_bits);
......
...@@ -537,6 +537,10 @@ int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) ...@@ -537,6 +537,10 @@ int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
radeon_vm_init(rdev, &fpriv->vm); radeon_vm_init(rdev, &fpriv->vm);
r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false);
if (r)
return r;
/* map the ib pool buffer read only into /* map the ib pool buffer read only into
* virtual address space */ * virtual address space */
bo_va = radeon_vm_bo_add(rdev, &fpriv->vm, bo_va = radeon_vm_bo_add(rdev, &fpriv->vm,
...@@ -544,6 +548,8 @@ int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) ...@@ -544,6 +548,8 @@ int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
r = radeon_vm_bo_set_addr(rdev, bo_va, RADEON_VA_IB_OFFSET, r = radeon_vm_bo_set_addr(rdev, bo_va, RADEON_VA_IB_OFFSET,
RADEON_VM_PAGE_READABLE | RADEON_VM_PAGE_READABLE |
RADEON_VM_PAGE_SNOOPED); RADEON_VM_PAGE_SNOOPED);
radeon_bo_unreserve(rdev->ring_tmp_bo.bo);
if (r) { if (r) {
radeon_vm_fini(rdev, &fpriv->vm); radeon_vm_fini(rdev, &fpriv->vm);
kfree(fpriv); kfree(fpriv);
......
...@@ -171,6 +171,8 @@ void radeon_uvd_fini(struct radeon_device *rdev) ...@@ -171,6 +171,8 @@ void radeon_uvd_fini(struct radeon_device *rdev)
radeon_bo_unref(&rdev->uvd.vcpu_bo); radeon_bo_unref(&rdev->uvd.vcpu_bo);
radeon_ring_fini(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX]);
release_firmware(rdev->uvd_fw); release_firmware(rdev->uvd_fw);
} }
......
...@@ -1955,9 +1955,9 @@ void rv770_fini(struct radeon_device *rdev) ...@@ -1955,9 +1955,9 @@ void rv770_fini(struct radeon_device *rdev)
radeon_wb_fini(rdev); radeon_wb_fini(rdev);
radeon_ib_pool_fini(rdev); radeon_ib_pool_fini(rdev);
radeon_irq_kms_fini(rdev); radeon_irq_kms_fini(rdev);
rv770_pcie_gart_fini(rdev);
uvd_v1_0_fini(rdev); uvd_v1_0_fini(rdev);
radeon_uvd_fini(rdev); radeon_uvd_fini(rdev);
rv770_pcie_gart_fini(rdev);
r600_vram_scratch_fini(rdev); r600_vram_scratch_fini(rdev);
radeon_gem_fini(rdev); radeon_gem_fini(rdev);
radeon_fence_driver_fini(rdev); radeon_fence_driver_fini(rdev);
......
...@@ -104,7 +104,7 @@ static void tegra_drm_context_free(struct tegra_drm_context *context) ...@@ -104,7 +104,7 @@ static void tegra_drm_context_free(struct tegra_drm_context *context)
static void tegra_drm_lastclose(struct drm_device *drm) static void tegra_drm_lastclose(struct drm_device *drm)
{ {
#ifdef CONFIG_TEGRA_DRM_FBDEV #ifdef CONFIG_DRM_TEGRA_FBDEV
struct tegra_drm *tegra = drm->dev_private; struct tegra_drm *tegra = drm->dev_private;
tegra_fbdev_restore_mode(tegra->fbdev); tegra_fbdev_restore_mode(tegra->fbdev);
......
...@@ -15,6 +15,7 @@ ...@@ -15,6 +15,7 @@
struct tegra_rgb { struct tegra_rgb {
struct tegra_output output; struct tegra_output output;
struct tegra_dc *dc; struct tegra_dc *dc;
bool enabled;
struct clk *clk_parent; struct clk *clk_parent;
struct clk *clk; struct clk *clk;
...@@ -89,6 +90,9 @@ static int tegra_output_rgb_enable(struct tegra_output *output) ...@@ -89,6 +90,9 @@ static int tegra_output_rgb_enable(struct tegra_output *output)
struct tegra_rgb *rgb = to_rgb(output); struct tegra_rgb *rgb = to_rgb(output);
unsigned long value; unsigned long value;
if (rgb->enabled)
return 0;
tegra_dc_write_regs(rgb->dc, rgb_enable, ARRAY_SIZE(rgb_enable)); tegra_dc_write_regs(rgb->dc, rgb_enable, ARRAY_SIZE(rgb_enable));
value = DE_SELECT_ACTIVE | DE_CONTROL_NORMAL; value = DE_SELECT_ACTIVE | DE_CONTROL_NORMAL;
...@@ -122,6 +126,8 @@ static int tegra_output_rgb_enable(struct tegra_output *output) ...@@ -122,6 +126,8 @@ static int tegra_output_rgb_enable(struct tegra_output *output)
tegra_dc_writel(rgb->dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL); tegra_dc_writel(rgb->dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
tegra_dc_writel(rgb->dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL); tegra_dc_writel(rgb->dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
rgb->enabled = true;
return 0; return 0;
} }
...@@ -130,6 +136,9 @@ static int tegra_output_rgb_disable(struct tegra_output *output) ...@@ -130,6 +136,9 @@ static int tegra_output_rgb_disable(struct tegra_output *output)
struct tegra_rgb *rgb = to_rgb(output); struct tegra_rgb *rgb = to_rgb(output);
unsigned long value; unsigned long value;
if (!rgb->enabled)
return 0;
value = tegra_dc_readl(rgb->dc, DC_CMD_DISPLAY_POWER_CONTROL); value = tegra_dc_readl(rgb->dc, DC_CMD_DISPLAY_POWER_CONTROL);
value &= ~(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE | value &= ~(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
PW4_ENABLE | PM0_ENABLE | PM1_ENABLE); PW4_ENABLE | PM0_ENABLE | PM1_ENABLE);
...@@ -144,6 +153,8 @@ static int tegra_output_rgb_disable(struct tegra_output *output) ...@@ -144,6 +153,8 @@ static int tegra_output_rgb_disable(struct tegra_output *output)
tegra_dc_write_regs(rgb->dc, rgb_disable, ARRAY_SIZE(rgb_disable)); tegra_dc_write_regs(rgb->dc, rgb_disable, ARRAY_SIZE(rgb_disable));
rgb->enabled = false;
return 0; return 0;
} }
......
...@@ -261,12 +261,7 @@ typedef enum SVGA3dSurfaceFormat { ...@@ -261,12 +261,7 @@ typedef enum SVGA3dSurfaceFormat {
/* Planar video formats. */ /* Planar video formats. */
SVGA3D_YV12 = 121, SVGA3D_YV12 = 121,
/* Shader constant formats. */ SVGA3D_FORMAT_MAX = 122,
SVGA3D_SURFACE_SHADERCONST_FLOAT = 122,
SVGA3D_SURFACE_SHADERCONST_INT = 123,
SVGA3D_SURFACE_SHADERCONST_BOOL = 124,
SVGA3D_FORMAT_MAX = 125,
} SVGA3dSurfaceFormat; } SVGA3dSurfaceFormat;
typedef uint32 SVGA3dColor; /* a, r, g, b */ typedef uint32 SVGA3dColor; /* a, r, g, b */
......
...@@ -40,7 +40,7 @@ ...@@ -40,7 +40,7 @@
#include <drm/ttm/ttm_module.h> #include <drm/ttm/ttm_module.h>
#include "vmwgfx_fence.h" #include "vmwgfx_fence.h"
#define VMWGFX_DRIVER_DATE "20121114" #define VMWGFX_DRIVER_DATE "20140228"
#define VMWGFX_DRIVER_MAJOR 2 #define VMWGFX_DRIVER_MAJOR 2
#define VMWGFX_DRIVER_MINOR 5 #define VMWGFX_DRIVER_MINOR 5
#define VMWGFX_DRIVER_PATCHLEVEL 0 #define VMWGFX_DRIVER_PATCHLEVEL 0
......
...@@ -188,18 +188,20 @@ static void vmw_takedown_otable_base(struct vmw_private *dev_priv, ...@@ -188,18 +188,20 @@ static void vmw_takedown_otable_base(struct vmw_private *dev_priv,
bo = otable->page_table->pt_bo; bo = otable->page_table->pt_bo;
cmd = vmw_fifo_reserve(dev_priv, sizeof(*cmd)); cmd = vmw_fifo_reserve(dev_priv, sizeof(*cmd));
if (unlikely(cmd == NULL)) if (unlikely(cmd == NULL)) {
DRM_ERROR("Failed reserving FIFO space for OTable setup.\n"); DRM_ERROR("Failed reserving FIFO space for OTable "
"takedown.\n");
memset(cmd, 0, sizeof(*cmd)); } else {
cmd->header.id = SVGA_3D_CMD_SET_OTABLE_BASE; memset(cmd, 0, sizeof(*cmd));
cmd->header.size = sizeof(cmd->body); cmd->header.id = SVGA_3D_CMD_SET_OTABLE_BASE;
cmd->body.type = type; cmd->header.size = sizeof(cmd->body);
cmd->body.baseAddress = 0; cmd->body.type = type;
cmd->body.sizeInBytes = 0; cmd->body.baseAddress = 0;
cmd->body.validSizeInBytes = 0; cmd->body.sizeInBytes = 0;
cmd->body.ptDepth = SVGA3D_MOBFMT_INVALID; cmd->body.validSizeInBytes = 0;
vmw_fifo_commit(dev_priv, sizeof(*cmd)); cmd->body.ptDepth = SVGA3D_MOBFMT_INVALID;
vmw_fifo_commit(dev_priv, sizeof(*cmd));
}
if (bo) { if (bo) {
int ret; int ret;
...@@ -562,11 +564,12 @@ void vmw_mob_unbind(struct vmw_private *dev_priv, ...@@ -562,11 +564,12 @@ void vmw_mob_unbind(struct vmw_private *dev_priv,
if (unlikely(cmd == NULL)) { if (unlikely(cmd == NULL)) {
DRM_ERROR("Failed reserving FIFO space for Memory " DRM_ERROR("Failed reserving FIFO space for Memory "
"Object unbinding.\n"); "Object unbinding.\n");
} else {
cmd->header.id = SVGA_3D_CMD_DESTROY_GB_MOB;
cmd->header.size = sizeof(cmd->body);
cmd->body.mobid = mob->id;
vmw_fifo_commit(dev_priv, sizeof(*cmd));
} }
cmd->header.id = SVGA_3D_CMD_DESTROY_GB_MOB;
cmd->header.size = sizeof(cmd->body);
cmd->body.mobid = mob->id;
vmw_fifo_commit(dev_priv, sizeof(*cmd));
if (bo) { if (bo) {
vmw_fence_single_bo(bo, NULL); vmw_fence_single_bo(bo, NULL);
ttm_bo_unreserve(bo); ttm_bo_unreserve(bo);
......
...@@ -427,8 +427,7 @@ int vmw_dmabuf_init(struct vmw_private *dev_priv, ...@@ -427,8 +427,7 @@ int vmw_dmabuf_init(struct vmw_private *dev_priv,
INIT_LIST_HEAD(&vmw_bo->res_list); INIT_LIST_HEAD(&vmw_bo->res_list);
ret = ttm_bo_init(bdev, &vmw_bo->base, size, ret = ttm_bo_init(bdev, &vmw_bo->base, size,
(user) ? ttm_bo_type_device : ttm_bo_type_device, placement,
ttm_bo_type_kernel, placement,
0, interruptible, 0, interruptible,
NULL, acc_size, NULL, bo_free); NULL, acc_size, NULL, bo_free);
return ret; return ret;
......
...@@ -538,7 +538,7 @@ int host1x_job_pin(struct host1x_job *job, struct device *dev) ...@@ -538,7 +538,7 @@ int host1x_job_pin(struct host1x_job *job, struct device *dev)
g->base = job->gather_addr_phys[i]; g->base = job->gather_addr_phys[i];
for (j = 0; j < job->num_gathers; j++) for (j = i + 1; j < job->num_gathers; j++)
if (job->gathers[j].bo == g->bo) if (job->gathers[j].bo == g->bo)
job->gathers[j].handled = true; job->gathers[j].handled = true;
......
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