Commit c5a107d3 authored by Thierry Reding's avatar Thierry Reding

drm/tegra: Add tegra_dc_setup_clock() helper

This is a small helper that performs the basic steps required by all
output drivers to prepare the display controller for use with a given
encoder.
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent d5bae6f3
......@@ -1092,6 +1092,26 @@ static int tegra_crtc_setup_clk(struct drm_crtc *crtc,
return 0;
}
int tegra_dc_setup_clock(struct tegra_dc *dc, struct clk *parent,
unsigned long pclk, unsigned int div)
{
u32 value;
int err;
err = clk_set_parent(dc->clk, parent);
if (err < 0) {
dev_err(dc->dev, "failed to set parent clock: %d\n", err);
return err;
}
DRM_DEBUG_KMS("rate: %lu, div: %u\n", clk_get_rate(dc->clk), div);
value = SHIFT_CLK_DIVIDER(div) | PIXEL_CLK_DIVIDER_PCD1;
tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL);
return 0;
}
static int tegra_crtc_mode_set(struct drm_crtc *crtc,
struct drm_display_mode *mode,
struct drm_display_mode *adjusted,
......
......@@ -178,6 +178,8 @@ void tegra_dc_enable_vblank(struct tegra_dc *dc);
void tegra_dc_disable_vblank(struct tegra_dc *dc);
void tegra_dc_cancel_page_flip(struct drm_crtc *crtc, struct drm_file *file);
void tegra_dc_commit(struct tegra_dc *dc);
int tegra_dc_setup_clock(struct tegra_dc *dc, struct clk *parent,
unsigned long pclk, unsigned int div);
struct tegra_output_ops {
int (*enable)(struct tegra_output *output);
......
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