drm/nouveau/sec2: switch to newer style interrupt handler

Ampere.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>

drivers/gpu/drm/nouveau/nvkm/engine/sec2/base.c

@@ -22,6 +22,7 @@
 #include "priv.h"
 
 #include <core/firmware.h>
+#include <subdev/mc.h>
 #include <subdev/timer.h>
 
 #include <nvfw/sec2.h>
@@ -35,13 +36,6 @@ nvkm_sec2_finimsg(void *priv, struct nvfw_falcon_msg *hdr)
 	return 0;
 }
 
-static void
-nvkm_sec2_intr(struct nvkm_engine *engine)
-{
-	struct nvkm_sec2 *sec2 = nvkm_sec2(engine);
-	sec2->func->intr(sec2);
-}
-
 static int
 nvkm_sec2_fini(struct nvkm_engine *engine, bool suspend)
 {
@@ -69,6 +63,8 @@ nvkm_sec2_fini(struct nvkm_engine *engine, bool suspend)
 		);
 	}
 
+	nvkm_inth_block(&subdev->inth);
+
 	nvkm_falcon_cmdq_fini(cmdq);
 	falcon->func->disable(falcon);
 	nvkm_falcon_put(falcon, subdev);
@@ -90,11 +86,24 @@ nvkm_sec2_init(struct nvkm_engine *engine)
 	nvkm_falcon_wr32(falcon, 0x014, 0xffffffff);
 	atomic_set(&sec2->initmsg, 0);
 	atomic_set(&sec2->running, 1);
+	nvkm_inth_allow(&subdev->inth);
 
 	nvkm_falcon_start(falcon);
 	return 0;
 }
 
+static int
+nvkm_sec2_oneinit(struct nvkm_engine *engine)
+{
+	struct nvkm_sec2 *sec2 = nvkm_sec2(engine);
+	struct nvkm_subdev *subdev = &sec2->engine.subdev;
+	struct nvkm_intr *intr = &sec2->engine.subdev.device->mc->intr;
+	enum nvkm_intr_type type = NVKM_INTR_SUBDEV;
+
+	return nvkm_inth_add(intr, type, NVKM_INTR_PRIO_NORMAL, subdev, sec2->func->intr,
+			     &subdev->inth);
+}
+
 static void *
 nvkm_sec2_dtor(struct nvkm_engine *engine)
 {
@@ -110,9 +119,9 @@ nvkm_sec2_dtor(struct nvkm_engine *engine)
 static const struct nvkm_engine_func
 nvkm_sec2 = {
 	.dtor = nvkm_sec2_dtor,
+	.oneinit = nvkm_sec2_oneinit,
 	.init = nvkm_sec2_init,
 	.fini = nvkm_sec2_fini,
-	.intr = nvkm_sec2_intr,
 };
 
 int

drivers/gpu/drm/nouveau/nvkm/engine/sec2/gp102.c

@@ -149,9 +149,10 @@ gp102_sec2_initmsg(struct nvkm_sec2 *sec2)
 	return 0;
 }
 
-void
-gp102_sec2_intr(struct nvkm_sec2 *sec2)
+irqreturn_t
+gp102_sec2_intr(struct nvkm_inth *inth)
 {
+	struct nvkm_sec2 *sec2 = container_of(inth, typeof(*sec2), engine.subdev.inth);
 	struct nvkm_subdev *subdev = &sec2->engine.subdev;
 	struct nvkm_falcon *falcon = &sec2->falcon;
 	u32 disp = nvkm_falcon_rd32(falcon, 0x01c);
@@ -185,6 +186,8 @@ gp102_sec2_intr(struct nvkm_sec2 *sec2)
 		nvkm_error(subdev, "unhandled intr %08x\n", intr);
 		nvkm_falcon_wr32(falcon, 0x004, intr);
 	}
+
+	return IRQ_HANDLED;
 }
 
 int

drivers/gpu/drm/nouveau/nvkm/engine/sec2/priv.h

@@ -7,11 +7,11 @@ struct nvkm_sec2_func {
 	const struct nvkm_falcon_func *flcn;
 	u8 unit_unload;
 	u8 unit_acr;
-	void (*intr)(struct nvkm_sec2 *);
+	irqreturn_t (*intr)(struct nvkm_inth *);
 	int (*initmsg)(struct nvkm_sec2 *);
 };
 
-void gp102_sec2_intr(struct nvkm_sec2 *);
+irqreturn_t gp102_sec2_intr(struct nvkm_inth *);
 int gp102_sec2_initmsg(struct nvkm_sec2 *);
 
 struct nvkm_sec2_fwif {

drivers/gpu/drm/nouveau/nvkm/subdev/mc/gp100.c

@@ -37,7 +37,8 @@ gp100_mc_intrs[] = {
 	{ NVKM_SUBDEV_I2C     , 0, 0, 0x00200000, true },
 	{ NVKM_SUBDEV_TIMER   , 0, 0, 0x00100000, true },
 	{ NVKM_SUBDEV_THERM   , 0, 0, 0x00040000, true },
-	{ NVKM_SUBDEV_TOP     , 0, 0, 0xffffffff, true },
+	{ NVKM_SUBDEV_TOP     , 0, 0, 0x00008000 },
+	{ NVKM_SUBDEV_TOP     , 0, 0, 0xffff7fff, true },
 	{},
 };