Commit c7e81462 authored by Maciej W. Rozycki's avatar Maciej W. Rozycki Committed by James Hogan

MIPS: ptrace: Fix PTRACE_PEEKUSR requests for 64-bit FGRs

Use 64-bit accesses for 64-bit floating-point general registers with
PTRACE_PEEKUSR, removing the truncation of their upper halves in the
FR=1 mode, caused by commit bbd426f5 ("MIPS: Simplify FP context
access"), which inadvertently switched them to using 32-bit accesses.

The PTRACE_POKEUSR side is fine as it's never been broken and continues
using 64-bit accesses.

Fixes: bbd426f5 ("MIPS: Simplify FP context access")
Signed-off-by: default avatarMaciej W. Rozycki <macro@mips.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org
Cc: <stable@vger.kernel.org> # 3.15+
Patchwork: https://patchwork.linux-mips.org/patch/19334/Signed-off-by: default avatarJames Hogan <jhogan@kernel.org>
parent 28e4213d
...@@ -818,7 +818,7 @@ long arch_ptrace(struct task_struct *child, long request, ...@@ -818,7 +818,7 @@ long arch_ptrace(struct task_struct *child, long request,
break; break;
} }
#endif #endif
tmp = get_fpr32(&fregs[addr - FPR_BASE], 0); tmp = get_fpr64(&fregs[addr - FPR_BASE], 0);
break; break;
case PC: case PC:
tmp = regs->cp0_epc; tmp = regs->cp0_epc;
......
...@@ -109,7 +109,7 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request, ...@@ -109,7 +109,7 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request,
addr & 1); addr & 1);
break; break;
} }
tmp = get_fpr32(&fregs[addr - FPR_BASE], 0); tmp = get_fpr64(&fregs[addr - FPR_BASE], 0);
break; break;
case PC: case PC:
tmp = regs->cp0_epc; tmp = regs->cp0_epc;
......
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