Commit c832da79 authored by Weili Qian's avatar Weili Qian Committed by Herbert Xu

crypto: hisilicon/qm - add UACCE_CMD_QM_SET_QP_INFO support

To be compatible with accelerator devices of different
versions, 'UACCE_CMD_QM_SET_QP_INFO' ioctl is added to obtain
queue information in userspace, including queue depth and buffer
description size.
Signed-off-by: default avatarWeili Qian <qianweili@huawei.com>
Signed-off-by: default avatarHerbert Xu <herbert@gondor.apana.org.au>
parent 129a9f34
...@@ -3430,6 +3430,7 @@ static long hisi_qm_uacce_ioctl(struct uacce_queue *q, unsigned int cmd, ...@@ -3430,6 +3430,7 @@ static long hisi_qm_uacce_ioctl(struct uacce_queue *q, unsigned int cmd,
unsigned long arg) unsigned long arg)
{ {
struct hisi_qp *qp = q->priv; struct hisi_qp *qp = q->priv;
struct hisi_qp_info qp_info;
struct hisi_qp_ctx qp_ctx; struct hisi_qp_ctx qp_ctx;
if (cmd == UACCE_CMD_QM_SET_QP_CTX) { if (cmd == UACCE_CMD_QM_SET_QP_CTX) {
...@@ -3446,11 +3447,25 @@ static long hisi_qm_uacce_ioctl(struct uacce_queue *q, unsigned int cmd, ...@@ -3446,11 +3447,25 @@ static long hisi_qm_uacce_ioctl(struct uacce_queue *q, unsigned int cmd,
if (copy_to_user((void __user *)arg, &qp_ctx, if (copy_to_user((void __user *)arg, &qp_ctx,
sizeof(struct hisi_qp_ctx))) sizeof(struct hisi_qp_ctx)))
return -EFAULT; return -EFAULT;
} else {
return -EINVAL; return 0;
} else if (cmd == UACCE_CMD_QM_SET_QP_INFO) {
if (copy_from_user(&qp_info, (void __user *)arg,
sizeof(struct hisi_qp_info)))
return -EFAULT;
qp_info.sqe_size = qp->qm->sqe_size;
qp_info.sq_depth = qp->sq_depth;
qp_info.cq_depth = qp->cq_depth;
if (copy_to_user((void __user *)arg, &qp_info,
sizeof(struct hisi_qp_info)))
return -EFAULT;
return 0;
} }
return 0; return -EINVAL;
} }
static const struct uacce_ops uacce_qm_ops = { static const struct uacce_ops uacce_qm_ops = {
......
...@@ -14,11 +14,26 @@ struct hisi_qp_ctx { ...@@ -14,11 +14,26 @@ struct hisi_qp_ctx {
__u16 qc_type; __u16 qc_type;
}; };
/**
* struct hisi_qp_info - User data for hisi qp.
* @sqe_size: Submission queue element size
* @sq_depth: The number of sqe
* @cq_depth: The number of cqe
* @reserved: Reserved data
*/
struct hisi_qp_info {
__u32 sqe_size;
__u16 sq_depth;
__u16 cq_depth;
__u64 reserved;
};
#define HISI_QM_API_VER_BASE "hisi_qm_v1" #define HISI_QM_API_VER_BASE "hisi_qm_v1"
#define HISI_QM_API_VER2_BASE "hisi_qm_v2" #define HISI_QM_API_VER2_BASE "hisi_qm_v2"
#define HISI_QM_API_VER3_BASE "hisi_qm_v3" #define HISI_QM_API_VER3_BASE "hisi_qm_v3"
/* UACCE_CMD_QM_SET_QP_CTX: Set qp algorithm type */ /* UACCE_CMD_QM_SET_QP_CTX: Set qp algorithm type */
#define UACCE_CMD_QM_SET_QP_CTX _IOWR('H', 10, struct hisi_qp_ctx) #define UACCE_CMD_QM_SET_QP_CTX _IOWR('H', 10, struct hisi_qp_ctx)
/* UACCE_CMD_QM_SET_QP_INFO: Set qp depth and BD size */
#define UACCE_CMD_QM_SET_QP_INFO _IOWR('H', 11, struct hisi_qp_info)
#endif #endif
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