Commit c9750481 authored by Jeffrey Deans's avatar Jeffrey Deans Committed by Ralf Baechle

MIPS: GIC: Move GIC_NUM_INTRS into platform irq.h

The value of GIC_NUM_INTRS is platform-specific. Using a default value
from gic.h will result in incorrect behaviour on some systems, so
require a suitable definition to be present in the platform's irq.h.
Signed-off-by: default avatarJeffrey Deans <jeffrey.deans@imgtec.com>
Signed-off-by: default avatarMarkos Chandras <markos.chandras@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/7373/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 822350bc
...@@ -14,6 +14,8 @@ ...@@ -14,6 +14,8 @@
#include <linux/bitmap.h> #include <linux/bitmap.h>
#include <linux/threads.h> #include <linux/threads.h>
#include <irq.h>
#undef GICISBYTELITTLEENDIAN #undef GICISBYTELITTLEENDIAN
/* Constants */ /* Constants */
...@@ -22,8 +24,6 @@ ...@@ -22,8 +24,6 @@
#define GIC_TRIG_EDGE 1 #define GIC_TRIG_EDGE 1
#define GIC_TRIG_LEVEL 0 #define GIC_TRIG_LEVEL 0
#define GIC_NUM_INTRS (24 + NR_CPUS * 2)
#define MSK(n) ((1 << (n)) - 1) #define MSK(n) ((1 << (n)) - 1)
#define REG32(addr) (*(volatile unsigned int *) (addr)) #define REG32(addr) (*(volatile unsigned int *) (addr))
#define REG(base, offs) REG32((unsigned long)(base) + offs##_##OFS) #define REG(base, offs) REG32((unsigned long)(base) + offs##_##OFS)
......
...@@ -2,6 +2,7 @@ ...@@ -2,6 +2,7 @@
#define __ASM_MACH_MIPS_IRQ_H #define __ASM_MACH_MIPS_IRQ_H
#define GIC_NUM_INTRS (24 + NR_CPUS * 2)
#define NR_IRQS 256 #define NR_IRQS 256
#include_next <irq.h> #include_next <irq.h>
......
#ifndef __ASM_MACH_MIPS_IRQ_H #ifndef __ASM_MACH_MIPS_IRQ_H
#define __ASM_MACH_MIPS_IRQ_H #define __ASM_MACH_MIPS_IRQ_H
#define GIC_NUM_INTRS (24 + NR_CPUS * 2)
#define NR_IRQS 256 #define NR_IRQS 256
......
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