Commit c9975337 authored by David S. Miller's avatar David S. Miller

Merge branch 'bcmgenet-next'

Petri Gynther says:

====================
net: bcmgenet: code cleanup

Five patches to clean up bcmgenet code:
1. add UMAC_IRQ_RXDMA_DONE and UMAC_IRQ_TXDMA_DONE
2. remove __bcmgenet_fini_dma()
3. fix bcmgenet_open()
4. add UMAC_IRQ_LINK_EVENT
5. fix the call to phy_mac_interrupt()
====================
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 3271e4f1 451e1ca2
...@@ -966,15 +966,13 @@ static void bcmgenet_free_cb(struct enet_cb *cb) ...@@ -966,15 +966,13 @@ static void bcmgenet_free_cb(struct enet_cb *cb)
static inline void bcmgenet_rx_ring16_int_disable(struct bcmgenet_rx_ring *ring) static inline void bcmgenet_rx_ring16_int_disable(struct bcmgenet_rx_ring *ring)
{ {
bcmgenet_intrl2_0_writel(ring->priv, bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_RXDMA_DONE,
UMAC_IRQ_RXDMA_BDONE | UMAC_IRQ_RXDMA_PDONE,
INTRL2_CPU_MASK_SET); INTRL2_CPU_MASK_SET);
} }
static inline void bcmgenet_rx_ring16_int_enable(struct bcmgenet_rx_ring *ring) static inline void bcmgenet_rx_ring16_int_enable(struct bcmgenet_rx_ring *ring)
{ {
bcmgenet_intrl2_0_writel(ring->priv, bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_RXDMA_DONE,
UMAC_IRQ_RXDMA_BDONE | UMAC_IRQ_RXDMA_PDONE,
INTRL2_CPU_MASK_CLEAR); INTRL2_CPU_MASK_CLEAR);
} }
...@@ -994,15 +992,13 @@ static inline void bcmgenet_rx_ring_int_enable(struct bcmgenet_rx_ring *ring) ...@@ -994,15 +992,13 @@ static inline void bcmgenet_rx_ring_int_enable(struct bcmgenet_rx_ring *ring)
static inline void bcmgenet_tx_ring16_int_disable(struct bcmgenet_tx_ring *ring) static inline void bcmgenet_tx_ring16_int_disable(struct bcmgenet_tx_ring *ring)
{ {
bcmgenet_intrl2_0_writel(ring->priv, bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_TXDMA_DONE,
UMAC_IRQ_TXDMA_BDONE | UMAC_IRQ_TXDMA_PDONE,
INTRL2_CPU_MASK_SET); INTRL2_CPU_MASK_SET);
} }
static inline void bcmgenet_tx_ring16_int_enable(struct bcmgenet_tx_ring *ring) static inline void bcmgenet_tx_ring16_int_enable(struct bcmgenet_tx_ring *ring)
{ {
bcmgenet_intrl2_0_writel(ring->priv, bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_TXDMA_DONE,
UMAC_IRQ_TXDMA_BDONE | UMAC_IRQ_TXDMA_PDONE,
INTRL2_CPU_MASK_CLEAR); INTRL2_CPU_MASK_CLEAR);
} }
...@@ -1727,16 +1723,16 @@ static int init_umac(struct bcmgenet_priv *priv) ...@@ -1727,16 +1723,16 @@ static int init_umac(struct bcmgenet_priv *priv)
bcmgenet_intr_disable(priv); bcmgenet_intr_disable(priv);
/* Enable Rx default queue 16 interrupts */ /* Enable Rx default queue 16 interrupts */
int0_enable |= (UMAC_IRQ_RXDMA_BDONE | UMAC_IRQ_RXDMA_PDONE); int0_enable |= UMAC_IRQ_RXDMA_DONE;
/* Enable Tx default queue 16 interrupts */ /* Enable Tx default queue 16 interrupts */
int0_enable |= (UMAC_IRQ_TXDMA_BDONE | UMAC_IRQ_TXDMA_PDONE); int0_enable |= UMAC_IRQ_TXDMA_DONE;
/* Monitor cable plug/unplugged event for internal PHY */ /* Monitor cable plug/unplugged event for internal PHY */
if (phy_is_internal(priv->phydev)) { if (phy_is_internal(priv->phydev)) {
int0_enable |= (UMAC_IRQ_LINK_DOWN | UMAC_IRQ_LINK_UP); int0_enable |= UMAC_IRQ_LINK_EVENT;
} else if (priv->ext_phy) { } else if (priv->ext_phy) {
int0_enable |= (UMAC_IRQ_LINK_DOWN | UMAC_IRQ_LINK_UP); int0_enable |= UMAC_IRQ_LINK_EVENT;
} else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) { } else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
reg = bcmgenet_bp_mc_get(priv); reg = bcmgenet_bp_mc_get(priv);
reg |= BIT(priv->hw_params->bp_in_en_shift); reg |= BIT(priv->hw_params->bp_in_en_shift);
...@@ -2177,10 +2173,13 @@ static int bcmgenet_dma_teardown(struct bcmgenet_priv *priv) ...@@ -2177,10 +2173,13 @@ static int bcmgenet_dma_teardown(struct bcmgenet_priv *priv)
return ret; return ret;
} }
static void __bcmgenet_fini_dma(struct bcmgenet_priv *priv) static void bcmgenet_fini_dma(struct bcmgenet_priv *priv)
{ {
int i; int i;
bcmgenet_fini_rx_napi(priv);
bcmgenet_fini_tx_napi(priv);
/* disable DMA */ /* disable DMA */
bcmgenet_dma_teardown(priv); bcmgenet_dma_teardown(priv);
...@@ -2196,14 +2195,6 @@ static void __bcmgenet_fini_dma(struct bcmgenet_priv *priv) ...@@ -2196,14 +2195,6 @@ static void __bcmgenet_fini_dma(struct bcmgenet_priv *priv)
kfree(priv->tx_cbs); kfree(priv->tx_cbs);
} }
static void bcmgenet_fini_dma(struct bcmgenet_priv *priv)
{
bcmgenet_fini_rx_napi(priv);
bcmgenet_fini_tx_napi(priv);
__bcmgenet_fini_dma(priv);
}
/* init_edma: Initialize DMA control register */ /* init_edma: Initialize DMA control register */
static int bcmgenet_init_dma(struct bcmgenet_priv *priv) static int bcmgenet_init_dma(struct bcmgenet_priv *priv)
{ {
...@@ -2280,10 +2271,10 @@ static void bcmgenet_irq_task(struct work_struct *work) ...@@ -2280,10 +2271,10 @@ static void bcmgenet_irq_task(struct work_struct *work)
/* Link UP/DOWN event */ /* Link UP/DOWN event */
if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) && if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) &&
(priv->irq0_stat & (UMAC_IRQ_LINK_UP|UMAC_IRQ_LINK_DOWN))) { (priv->irq0_stat & UMAC_IRQ_LINK_EVENT)) {
phy_mac_interrupt(priv->phydev, phy_mac_interrupt(priv->phydev,
priv->irq0_stat & UMAC_IRQ_LINK_UP); !!(priv->irq0_stat & UMAC_IRQ_LINK_UP));
priv->irq0_stat &= ~(UMAC_IRQ_LINK_UP|UMAC_IRQ_LINK_DOWN); priv->irq0_stat &= ~UMAC_IRQ_LINK_EVENT;
} }
} }
...@@ -2353,7 +2344,7 @@ static irqreturn_t bcmgenet_isr0(int irq, void *dev_id) ...@@ -2353,7 +2344,7 @@ static irqreturn_t bcmgenet_isr0(int irq, void *dev_id)
netif_dbg(priv, intr, priv->dev, netif_dbg(priv, intr, priv->dev,
"IRQ=0x%x\n", priv->irq0_stat); "IRQ=0x%x\n", priv->irq0_stat);
if (priv->irq0_stat & (UMAC_IRQ_RXDMA_BDONE | UMAC_IRQ_RXDMA_PDONE)) { if (priv->irq0_stat & UMAC_IRQ_RXDMA_DONE) {
rx_ring = &priv->rx_rings[DESC_INDEX]; rx_ring = &priv->rx_rings[DESC_INDEX];
if (likely(napi_schedule_prep(&rx_ring->napi))) { if (likely(napi_schedule_prep(&rx_ring->napi))) {
...@@ -2362,7 +2353,7 @@ static irqreturn_t bcmgenet_isr0(int irq, void *dev_id) ...@@ -2362,7 +2353,7 @@ static irqreturn_t bcmgenet_isr0(int irq, void *dev_id)
} }
} }
if (priv->irq0_stat & (UMAC_IRQ_TXDMA_BDONE | UMAC_IRQ_TXDMA_PDONE)) { if (priv->irq0_stat & UMAC_IRQ_TXDMA_DONE) {
tx_ring = &priv->tx_rings[DESC_INDEX]; tx_ring = &priv->tx_rings[DESC_INDEX];
if (likely(napi_schedule_prep(&tx_ring->napi))) { if (likely(napi_schedule_prep(&tx_ring->napi))) {
...@@ -2373,8 +2364,7 @@ static irqreturn_t bcmgenet_isr0(int irq, void *dev_id) ...@@ -2373,8 +2364,7 @@ static irqreturn_t bcmgenet_isr0(int irq, void *dev_id)
if (priv->irq0_stat & (UMAC_IRQ_PHY_DET_R | if (priv->irq0_stat & (UMAC_IRQ_PHY_DET_R |
UMAC_IRQ_PHY_DET_F | UMAC_IRQ_PHY_DET_F |
UMAC_IRQ_LINK_UP | UMAC_IRQ_LINK_EVENT |
UMAC_IRQ_LINK_DOWN |
UMAC_IRQ_HFB_SM | UMAC_IRQ_HFB_SM |
UMAC_IRQ_HFB_MM | UMAC_IRQ_HFB_MM |
UMAC_IRQ_MPD_R)) { UMAC_IRQ_MPD_R)) {
...@@ -2675,7 +2665,7 @@ static int bcmgenet_open(struct net_device *dev) ...@@ -2675,7 +2665,7 @@ static int bcmgenet_open(struct net_device *dev)
ret = bcmgenet_init_dma(priv); ret = bcmgenet_init_dma(priv);
if (ret) { if (ret) {
netdev_err(dev, "failed to initialize DMA\n"); netdev_err(dev, "failed to initialize DMA\n");
goto err_fini_dma; goto err_clk_disable;
} }
/* Always enable ring 16 - descriptor ring */ /* Always enable ring 16 - descriptor ring */
......
...@@ -293,6 +293,7 @@ struct bcmgenet_mib_counters { ...@@ -293,6 +293,7 @@ struct bcmgenet_mib_counters {
#define UMAC_IRQ_PHY_DET_F (1 << 3) #define UMAC_IRQ_PHY_DET_F (1 << 3)
#define UMAC_IRQ_LINK_UP (1 << 4) #define UMAC_IRQ_LINK_UP (1 << 4)
#define UMAC_IRQ_LINK_DOWN (1 << 5) #define UMAC_IRQ_LINK_DOWN (1 << 5)
#define UMAC_IRQ_LINK_EVENT (UMAC_IRQ_LINK_UP | UMAC_IRQ_LINK_DOWN)
#define UMAC_IRQ_UMAC (1 << 6) #define UMAC_IRQ_UMAC (1 << 6)
#define UMAC_IRQ_UMAC_TSV (1 << 7) #define UMAC_IRQ_UMAC_TSV (1 << 7)
#define UMAC_IRQ_TBUF_UNDERRUN (1 << 8) #define UMAC_IRQ_TBUF_UNDERRUN (1 << 8)
...@@ -303,9 +304,13 @@ struct bcmgenet_mib_counters { ...@@ -303,9 +304,13 @@ struct bcmgenet_mib_counters {
#define UMAC_IRQ_RXDMA_MBDONE (1 << 13) #define UMAC_IRQ_RXDMA_MBDONE (1 << 13)
#define UMAC_IRQ_RXDMA_PDONE (1 << 14) #define UMAC_IRQ_RXDMA_PDONE (1 << 14)
#define UMAC_IRQ_RXDMA_BDONE (1 << 15) #define UMAC_IRQ_RXDMA_BDONE (1 << 15)
#define UMAC_IRQ_RXDMA_DONE (UMAC_IRQ_RXDMA_PDONE | \
UMAC_IRQ_RXDMA_BDONE)
#define UMAC_IRQ_TXDMA_MBDONE (1 << 16) #define UMAC_IRQ_TXDMA_MBDONE (1 << 16)
#define UMAC_IRQ_TXDMA_PDONE (1 << 17) #define UMAC_IRQ_TXDMA_PDONE (1 << 17)
#define UMAC_IRQ_TXDMA_BDONE (1 << 18) #define UMAC_IRQ_TXDMA_BDONE (1 << 18)
#define UMAC_IRQ_TXDMA_DONE (UMAC_IRQ_TXDMA_PDONE | \
UMAC_IRQ_TXDMA_BDONE)
/* Only valid for GENETv3+ */ /* Only valid for GENETv3+ */
#define UMAC_IRQ_MDIO_DONE (1 << 23) #define UMAC_IRQ_MDIO_DONE (1 << 23)
#define UMAC_IRQ_MDIO_ERROR (1 << 24) #define UMAC_IRQ_MDIO_ERROR (1 << 24)
......
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