Commit c9dcd56f authored by Arnd Bergmann's avatar Arnd Bergmann

spi: remove s3c24xx driver

The s3c24xx platform was removed,s o there are no remaining users
for its spi driver.
Reviewed-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parent 20ab62c4
...@@ -18450,7 +18450,6 @@ S: Maintained ...@@ -18450,7 +18450,6 @@ S: Maintained
F: Documentation/devicetree/bindings/spi/samsung,spi*.yaml F: Documentation/devicetree/bindings/spi/samsung,spi*.yaml
F: drivers/spi/spi-s3c* F: drivers/spi/spi-s3c*
F: include/linux/platform_data/spi-s3c64xx.h F: include/linux/platform_data/spi-s3c64xx.h
F: include/linux/spi/s3c24xx-fiq.h
SAMSUNG SXGBE DRIVERS SAMSUNG SXGBE DRIVERS
M: Byungho An <bh74.an@samsung.com> M: Byungho An <bh74.an@samsung.com>
......
...@@ -838,24 +838,6 @@ config SPI_QCOM_GENI ...@@ -838,24 +838,6 @@ config SPI_QCOM_GENI
This driver can also be built as a module. If so, the module This driver can also be built as a module. If so, the module
will be called spi-geni-qcom. will be called spi-geni-qcom.
config SPI_S3C24XX
tristate "Samsung S3C24XX series SPI"
depends on ARCH_S3C24XX
select SPI_BITBANG
help
SPI driver for Samsung S3C24XX series ARM SoCs
config SPI_S3C24XX_FIQ
bool "S3C24XX driver with FIQ pseudo-DMA"
depends on SPI_S3C24XX
select FIQ
help
Enable FIQ support for the S3C24XX SPI driver to provide pseudo
DMA by using the fast-interrupt request framework, This allows
the driver to get DMA-like performance when there are either
no free DMA channels, or when doing transfers that required both
TX and RX data paths.
config SPI_S3C64XX config SPI_S3C64XX
tristate "Samsung S3C64XX/Exynos SoC series type SPI" tristate "Samsung S3C64XX/Exynos SoC series type SPI"
depends on (PLAT_SAMSUNG || ARCH_S5PV210 || ARCH_EXYNOS || COMPILE_TEST) depends on (PLAT_SAMSUNG || ARCH_S5PV210 || ARCH_EXYNOS || COMPILE_TEST)
......
...@@ -111,8 +111,6 @@ obj-$(CONFIG_SPI_RB4XX) += spi-rb4xx.o ...@@ -111,8 +111,6 @@ obj-$(CONFIG_SPI_RB4XX) += spi-rb4xx.o
obj-$(CONFIG_MACH_REALTEK_RTL) += spi-realtek-rtl.o obj-$(CONFIG_MACH_REALTEK_RTL) += spi-realtek-rtl.o
obj-$(CONFIG_SPI_RPCIF) += spi-rpc-if.o obj-$(CONFIG_SPI_RPCIF) += spi-rpc-if.o
obj-$(CONFIG_SPI_RSPI) += spi-rspi.o obj-$(CONFIG_SPI_RSPI) += spi-rspi.o
obj-$(CONFIG_SPI_S3C24XX) += spi-s3c24xx-hw.o
spi-s3c24xx-hw-y := spi-s3c24xx.o
obj-$(CONFIG_SPI_S3C64XX) += spi-s3c64xx.o obj-$(CONFIG_SPI_S3C64XX) += spi-s3c64xx.o
obj-$(CONFIG_SPI_SC18IS602) += spi-sc18is602.o obj-$(CONFIG_SPI_SC18IS602) += spi-sc18is602.o
obj-$(CONFIG_SPI_SH) += spi-sh.o obj-$(CONFIG_SPI_SH) += spi-sh.o
......
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2004 Fetron GmbH
*
* S3C2410 SPI register definition
*/
#ifndef __SPI_S3C2410_H
#define __SPI_S3C2410_H
#define S3C2410_SPCON (0x00)
#define S3C2410_SPCON_SMOD_DMA (2 << 5) /* DMA mode */
#define S3C2410_SPCON_SMOD_INT (1 << 5) /* interrupt mode */
#define S3C2410_SPCON_SMOD_POLL (0 << 5) /* polling mode */
#define S3C2410_SPCON_ENSCK (1 << 4) /* Enable SCK */
#define S3C2410_SPCON_MSTR (1 << 3) /* Master:1, Slave:0 select */
#define S3C2410_SPCON_CPOL_HIGH (1 << 2) /* Clock polarity select */
#define S3C2410_SPCON_CPOL_LOW (0 << 2) /* Clock polarity select */
#define S3C2410_SPCON_CPHA_FMTB (1 << 1) /* Clock Phase Select */
#define S3C2410_SPCON_CPHA_FMTA (0 << 1) /* Clock Phase Select */
#define S3C2410_SPSTA (0x04)
#define S3C2410_SPSTA_DCOL (1 << 2) /* Data Collision Error */
#define S3C2410_SPSTA_MULD (1 << 1) /* Multi Master Error */
#define S3C2410_SPSTA_READY (1 << 0) /* Data Tx/Rx ready */
#define S3C2412_SPSTA_READY_ORG (1 << 3)
#define S3C2410_SPPIN (0x08)
#define S3C2410_SPPIN_ENMUL (1 << 2) /* Multi Master Error detect */
#define S3C2410_SPPIN_RESERVED (1 << 1)
#define S3C2410_SPPIN_KEEP (1 << 0) /* Master Out keep */
#define S3C2410_SPPRE (0x0C)
#define S3C2410_SPTDAT (0x10)
#define S3C2410_SPRDAT (0x14)
#endif /* __SPI_S3C2410_H */
This diff is collapsed.
/* SPDX-License-Identifier: GPL-2.0-only */
/* linux/drivers/spi/spi_s3c24xx_fiq.h
*
* Copyright 2009 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* S3C24XX SPI - FIQ pseudo-DMA transfer support
*/
#ifndef __LINUX_SPI_S3C24XX_FIQ_H
#define __LINUX_SPI_S3C24XX_FIQ_H __FILE__
/* We have R8 through R13 to play with */
#ifdef __ASSEMBLY__
#define __REG_NR(x) r##x
#else
extern struct spi_fiq_code s3c24xx_spi_fiq_txrx;
extern struct spi_fiq_code s3c24xx_spi_fiq_tx;
extern struct spi_fiq_code s3c24xx_spi_fiq_rx;
#define __REG_NR(x) (x)
#endif
#define fiq_rspi __REG_NR(8)
#define fiq_rtmp __REG_NR(9)
#define fiq_rrx __REG_NR(10)
#define fiq_rtx __REG_NR(11)
#define fiq_rcount __REG_NR(12)
#define fiq_rirq __REG_NR(13)
#endif /* __LINUX_SPI_S3C24XX_FIQ_H */
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2006 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* S3C2410 - SPI Controller platform_device info
*/
#ifndef __LINUX_SPI_S3C24XX_H
#define __LINUX_SPI_S3C24XX_H __FILE__
struct s3c2410_spi_info {
unsigned int num_cs; /* total chipselects */
int bus_num; /* bus number to use. */
unsigned int use_fiq:1; /* use fiq */
};
extern int s3c24xx_set_fiq(unsigned int irq, u32 *ack_ptr, bool on);
#endif /* __LINUX_SPI_S3C24XX_H */
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