Commit ca850f2b authored by Guangbin Huang's avatar Guangbin Huang Committed by David S. Miller

net: hns3: add support to query device capability

In order to improve code maintainability and compatibility,
add support to query the device capability by expanding the
existing version query command. The device capability refers
to the features supported by the device.
Signed-off-by: default avatarGuangbin Huang <huangguangbin2@huawei.com>
Signed-off-by: default avatarHuazhong Tan <tanhuazhong@huawei.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 9b56d9a5
......@@ -2076,15 +2076,6 @@ static void hns3_disable_sriov(struct pci_dev *pdev)
pci_disable_sriov(pdev);
}
static void hns3_get_dev_capability(struct pci_dev *pdev,
struct hnae3_ae_dev *ae_dev)
{
if (pdev->revision >= 0x21) {
hnae3_set_bit(ae_dev->flag, HNAE3_DEV_SUPPORT_FD_B, 1);
hnae3_set_bit(ae_dev->flag, HNAE3_DEV_SUPPORT_GRO_B, 1);
}
}
/* hns3_probe - Device initialization routine
* @pdev: PCI device information struct
* @ent: entry in hns3_pci_tbl
......@@ -2106,7 +2097,6 @@ static int hns3_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
ae_dev->pdev = pdev;
ae_dev->flag = ent->driver_data;
hns3_get_dev_capability(pdev, ae_dev);
pci_set_drvdata(pdev, ae_dev);
ret = hnae3_register_ae_dev(ae_dev);
......
......@@ -330,7 +330,8 @@ int hclge_cmd_send(struct hclge_hw *hw, struct hclge_desc *desc, int num)
return retval;
}
static enum hclge_cmd_status hclge_cmd_query_version(struct hclge_dev *hdev)
static enum hclge_cmd_status
hclge_cmd_query_version_and_capability(struct hclge_dev *hdev)
{
struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
struct hclge_query_version_cmd *resp;
......@@ -350,6 +351,12 @@ static enum hclge_cmd_status hclge_cmd_query_version(struct hclge_dev *hdev)
HNAE3_PCI_REVISION_BIT_SIZE;
ae_dev->dev_version |= hdev->pdev->revision;
if (!resp->caps[0] &&
ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) {
hnae3_set_bit(ae_dev->flag, HNAE3_DEV_SUPPORT_FD_B, 1);
hnae3_set_bit(ae_dev->flag, HNAE3_DEV_SUPPORT_GRO_B, 1);
}
return ret;
}
......@@ -436,10 +443,12 @@ int hclge_cmd_init(struct hclge_dev *hdev)
goto err_cmd_init;
}
ret = hclge_cmd_query_version(hdev);
/* get version and device capabilities */
ret = hclge_cmd_query_version_and_capability(hdev);
if (ret) {
dev_err(&hdev->pdev->dev,
"failed to query version ret=%d\n", ret);
"failed to query version and capabilities, ret = %d\n",
ret);
goto err_cmd_init;
}
......
......@@ -362,10 +362,12 @@ struct hclge_rx_priv_buff_cmd {
u8 rsv[6];
};
#define HCLGE_QUERY_CAP_LENGTH 3
struct hclge_query_version_cmd {
__le32 firmware;
__le32 hardware;
__le32 rsv[4];
__le32 rsv;
__le32 caps[HCLGE_QUERY_CAP_LENGTH]; /* capabilities of device */
};
#define HCLGE_RX_PRIV_EN_B 15
......
......@@ -313,7 +313,7 @@ int hclgevf_cmd_send(struct hclgevf_hw *hw, struct hclgevf_desc *desc, int num)
return status;
}
static int hclgevf_cmd_query_version(struct hclgevf_dev *hdev)
static int hclgevf_cmd_query_version_and_capability(struct hclgevf_dev *hdev)
{
struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
struct hclgevf_query_version_cmd *resp;
......@@ -333,6 +333,12 @@ static int hclgevf_cmd_query_version(struct hclgevf_dev *hdev)
HNAE3_PCI_REVISION_BIT_SIZE;
ae_dev->dev_version |= hdev->pdev->revision;
if (!resp->caps[0] &&
ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2) {
hnae3_set_bit(ae_dev->flag, HNAE3_DEV_SUPPORT_FD_B, 1);
hnae3_set_bit(ae_dev->flag, HNAE3_DEV_SUPPORT_GRO_B, 1);
}
return status;
}
......@@ -400,9 +406,11 @@ int hclgevf_cmd_init(struct hclgevf_dev *hdev)
goto err_cmd_init;
}
ret = hclgevf_cmd_query_version(hdev);
/* get version and device capabilities */
ret = hclgevf_cmd_query_version_and_capability(hdev);
if (ret) {
dev_err(&hdev->pdev->dev, "failed(%d) to query version\n", ret);
dev_err(&hdev->pdev->dev,
"failed to query version and capabilities, ret = %d\n", ret);
goto err_cmd_init;
}
......
......@@ -141,10 +141,12 @@ struct hclgevf_ctrl_vector_chain {
u8 resv;
};
#define HCLGEVF_QUERY_CAP_LENGTH 3
struct hclgevf_query_version_cmd {
__le32 firmware;
__le32 hardware;
__le32 rsv[4];
__le32 rsv;
__le32 caps[HCLGEVF_QUERY_CAP_LENGTH]; /* capabilities of device */
};
#define HCLGEVF_MSIX_OFT_ROCEE_S 0
......
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