Commit cb626376 authored by James Ogletree's avatar James Ogletree Committed by Lee Jones

mfd: cs40l50: Add support for CS40L50 core driver

Introduce support for Cirrus Logic Device CS40L50: a
haptic driver with waveform memory, integrated DSP,
and closed-loop algorithms.

The MFD component registers and initializes the device.
Signed-off-by: default avatarJames Ogletree <jogletre@opensource.cirrus.com>
Reviewed-by: default avatarJeff LaBundy <jeff@labundy.com>
Link: https://lore.kernel.org/r/20240620161745.2312359-4-jogletre@opensource.cirrus.comSigned-off-by: default avatarLee Jones <lee@kernel.org>
parent 2fab5aba
......@@ -5213,6 +5213,8 @@ M: Ben Bright <ben.bright@cirrus.com>
L: patches@opensource.cirrus.com
S: Supported
F: Documentation/devicetree/bindings/input/cirrus,cs40l50.yaml
F: drivers/mfd/cs40l*
F: include/linux/mfd/cs40l*
CIRRUS LOGIC DSP FIRMWARE DRIVER
M: Simon Trimmer <simont@opensource.cirrus.com>
......
......@@ -2243,6 +2243,36 @@ config MCP_UCB1200_TS
endmenu
config MFD_CS40L50_CORE
tristate
select MFD_CORE
select FW_CS_DSP
select REGMAP_IRQ
config MFD_CS40L50_I2C
tristate "Cirrus Logic CS40L50 (I2C)"
select REGMAP_I2C
select MFD_CS40L50_CORE
depends on I2C
help
Select this to support the Cirrus Logic CS40L50 Haptic
Driver over I2C.
This driver can be built as a module. If built as a module it will be
called "cs40l50-i2c".
config MFD_CS40L50_SPI
tristate "Cirrus Logic CS40L50 (SPI)"
select REGMAP_SPI
select MFD_CS40L50_CORE
depends on SPI
help
Select this to support the Cirrus Logic CS40L50 Haptic
Driver over SPI.
This driver can be built as a module. If built as a module it will be
called "cs40l50-spi".
config MFD_VEXPRESS_SYSREG
tristate "Versatile Express System Registers"
depends on VEXPRESS_CONFIG && GPIOLIB
......
......@@ -88,6 +88,10 @@ obj-$(CONFIG_MFD_MADERA) += madera.o
obj-$(CONFIG_MFD_MADERA_I2C) += madera-i2c.o
obj-$(CONFIG_MFD_MADERA_SPI) += madera-spi.o
obj-$(CONFIG_MFD_CS40L50_CORE) += cs40l50-core.o
obj-$(CONFIG_MFD_CS40L50_I2C) += cs40l50-i2c.o
obj-$(CONFIG_MFD_CS40L50_SPI) += cs40l50-spi.o
obj-$(CONFIG_TPS6105X) += tps6105x.o
obj-$(CONFIG_TPS65010) += tps65010.o
obj-$(CONFIG_TPS6507X) += tps6507x.o
......
This diff is collapsed.
// SPDX-License-Identifier: GPL-2.0
/*
* CS40L50 Advanced Haptic Driver with waveform memory,
* integrated DSP, and closed-loop algorithms
*
* Copyright 2024 Cirrus Logic, Inc.
*
* Author: James Ogletree <james.ogletree@cirrus.com>
*/
#include <linux/i2c.h>
#include <linux/mfd/cs40l50.h>
static int cs40l50_i2c_probe(struct i2c_client *i2c)
{
struct cs40l50 *cs40l50;
cs40l50 = devm_kzalloc(&i2c->dev, sizeof(*cs40l50), GFP_KERNEL);
if (!cs40l50)
return -ENOMEM;
i2c_set_clientdata(i2c, cs40l50);
cs40l50->dev = &i2c->dev;
cs40l50->irq = i2c->irq;
cs40l50->regmap = devm_regmap_init_i2c(i2c, &cs40l50_regmap);
if (IS_ERR(cs40l50->regmap))
return dev_err_probe(cs40l50->dev, PTR_ERR(cs40l50->regmap),
"Failed to initialize register map\n");
return cs40l50_probe(cs40l50);
}
static void cs40l50_i2c_remove(struct i2c_client *i2c)
{
struct cs40l50 *cs40l50 = i2c_get_clientdata(i2c);
cs40l50_remove(cs40l50);
}
static const struct i2c_device_id cs40l50_id_i2c[] = {
{ "cs40l50" },
{}
};
MODULE_DEVICE_TABLE(i2c, cs40l50_id_i2c);
static const struct of_device_id cs40l50_of_match[] = {
{ .compatible = "cirrus,cs40l50" },
{}
};
MODULE_DEVICE_TABLE(of, cs40l50_of_match);
static struct i2c_driver cs40l50_i2c_driver = {
.driver = {
.name = "cs40l50",
.of_match_table = cs40l50_of_match,
.pm = pm_ptr(&cs40l50_pm_ops),
},
.id_table = cs40l50_id_i2c,
.probe = cs40l50_i2c_probe,
.remove = cs40l50_i2c_remove,
};
module_i2c_driver(cs40l50_i2c_driver);
MODULE_DESCRIPTION("CS40L50 I2C Driver");
MODULE_AUTHOR("James Ogletree, Cirrus Logic Inc. <james.ogletree@cirrus.com>");
MODULE_LICENSE("GPL");
// SPDX-License-Identifier: GPL-2.0
/*
* CS40L50 Advanced Haptic Driver with waveform memory,
* integrated DSP, and closed-loop algorithms
*
* Copyright 2024 Cirrus Logic, Inc.
*
* Author: James Ogletree <james.ogletree@cirrus.com>
*/
#include <linux/mfd/cs40l50.h>
#include <linux/spi/spi.h>
static int cs40l50_spi_probe(struct spi_device *spi)
{
struct cs40l50 *cs40l50;
cs40l50 = devm_kzalloc(&spi->dev, sizeof(*cs40l50), GFP_KERNEL);
if (!cs40l50)
return -ENOMEM;
spi_set_drvdata(spi, cs40l50);
cs40l50->dev = &spi->dev;
cs40l50->irq = spi->irq;
cs40l50->regmap = devm_regmap_init_spi(spi, &cs40l50_regmap);
if (IS_ERR(cs40l50->regmap))
return dev_err_probe(cs40l50->dev, PTR_ERR(cs40l50->regmap),
"Failed to initialize register map\n");
return cs40l50_probe(cs40l50);
}
static void cs40l50_spi_remove(struct spi_device *spi)
{
struct cs40l50 *cs40l50 = spi_get_drvdata(spi);
cs40l50_remove(cs40l50);
}
static const struct spi_device_id cs40l50_id_spi[] = {
{ "cs40l50" },
{}
};
MODULE_DEVICE_TABLE(spi, cs40l50_id_spi);
static const struct of_device_id cs40l50_of_match[] = {
{ .compatible = "cirrus,cs40l50" },
{}
};
MODULE_DEVICE_TABLE(of, cs40l50_of_match);
static struct spi_driver cs40l50_spi_driver = {
.driver = {
.name = "cs40l50",
.of_match_table = cs40l50_of_match,
.pm = pm_ptr(&cs40l50_pm_ops),
},
.id_table = cs40l50_id_spi,
.probe = cs40l50_spi_probe,
.remove = cs40l50_spi_remove,
};
module_spi_driver(cs40l50_spi_driver);
MODULE_DESCRIPTION("CS40L50 SPI Driver");
MODULE_AUTHOR("James Ogletree, Cirrus Logic Inc. <james.ogletree@cirrus.com>");
MODULE_LICENSE("GPL");
/* SPDX-License-Identifier: GPL-2.0
*
* CS40L50 Advanced Haptic Driver with waveform memory,
* integrated DSP, and closed-loop algorithms
*
* Copyright 2024 Cirrus Logic, Inc.
*
* Author: James Ogletree <james.ogletree@cirrus.com>
*/
#ifndef __MFD_CS40L50_H__
#define __MFD_CS40L50_H__
#include <linux/firmware/cirrus/cs_dsp.h>
#include <linux/gpio/consumer.h>
#include <linux/pm.h>
#include <linux/regmap.h>
/* Power Supply Configuration */
#define CS40L50_BLOCK_ENABLES2 0x201C
#define CS40L50_ERR_RLS 0x2034
#define CS40L50_BST_LPMODE_SEL 0x3810
#define CS40L50_DCM_LOW_POWER 0x1
#define CS40L50_OVERTEMP_WARN 0x4000010
/* Interrupts */
#define CS40L50_IRQ1_INT_1 0xE010
#define CS40L50_IRQ1_BASE CS40L50_IRQ1_INT_1
#define CS40L50_IRQ1_INT_2 0xE014
#define CS40L50_IRQ1_INT_8 0xE02C
#define CS40L50_IRQ1_INT_9 0xE030
#define CS40L50_IRQ1_INT_10 0xE034
#define CS40L50_IRQ1_INT_18 0xE054
#define CS40L50_IRQ1_MASK_1 0xE090
#define CS40L50_IRQ1_MASK_2 0xE094
#define CS40L50_IRQ1_MASK_20 0xE0DC
#define CS40L50_IRQ1_INT_1_OFFSET (CS40L50_IRQ1_INT_1 - CS40L50_IRQ1_BASE)
#define CS40L50_IRQ1_INT_2_OFFSET (CS40L50_IRQ1_INT_2 - CS40L50_IRQ1_BASE)
#define CS40L50_IRQ1_INT_8_OFFSET (CS40L50_IRQ1_INT_8 - CS40L50_IRQ1_BASE)
#define CS40L50_IRQ1_INT_9_OFFSET (CS40L50_IRQ1_INT_9 - CS40L50_IRQ1_BASE)
#define CS40L50_IRQ1_INT_10_OFFSET (CS40L50_IRQ1_INT_10 - CS40L50_IRQ1_BASE)
#define CS40L50_IRQ1_INT_18_OFFSET (CS40L50_IRQ1_INT_18 - CS40L50_IRQ1_BASE)
#define CS40L50_IRQ_MASK_2_OVERRIDE 0xFFDF7FFF
#define CS40L50_IRQ_MASK_20_OVERRIDE 0x15C01000
#define CS40L50_AMP_SHORT_MASK BIT(31)
#define CS40L50_DSP_QUEUE_MASK BIT(21)
#define CS40L50_TEMP_ERR_MASK BIT(31)
#define CS40L50_BST_UVP_MASK BIT(6)
#define CS40L50_BST_SHORT_MASK BIT(7)
#define CS40L50_BST_ILIMIT_MASK BIT(18)
#define CS40L50_UVLO_VDDBATT_MASK BIT(16)
#define CS40L50_GLOBAL_ERROR_MASK BIT(15)
enum cs40l50_irq_list {
CS40L50_DSP_QUEUE_IRQ,
CS40L50_GLOBAL_ERROR_IRQ,
CS40L50_UVLO_VDDBATT_IRQ,
CS40L50_BST_ILIMIT_IRQ,
CS40L50_BST_SHORT_IRQ,
CS40L50_BST_UVP_IRQ,
CS40L50_TEMP_ERR_IRQ,
CS40L50_AMP_SHORT_IRQ,
};
/* DSP */
#define CS40L50_XMEM_PACKED_0 0x2000000
#define CS40L50_XMEM_UNPACKED24_0 0x2800000
#define CS40L50_SYS_INFO_ID 0x25E0000
#define CS40L50_DSP_QUEUE_WT 0x28042C8
#define CS40L50_DSP_QUEUE_RD 0x28042CC
#define CS40L50_NUM_WAVES 0x2805C18
#define CS40L50_CORE_BASE 0x2B80000
#define CS40L50_YMEM_PACKED_0 0x2C00000
#define CS40L50_YMEM_UNPACKED24_0 0x3400000
#define CS40L50_PMEM_0 0x3800000
#define CS40L50_DSP_POLL_US 1000
#define CS40L50_DSP_TIMEOUT_COUNT 100
#define CS40L50_RESET_PULSE_US 2200
#define CS40L50_CP_READY_US 3100
#define CS40L50_AUTOSUSPEND_MS 2000
#define CS40L50_PM_ALGO 0x9F206
#define CS40L50_GLOBAL_ERR_RLS_SET BIT(11)
#define CS40L50_GLOBAL_ERR_RLS_CLEAR 0
enum cs40l50_wseqs {
CS40L50_PWR_ON,
CS40L50_STANDBY,
CS40L50_ACTIVE,
CS40L50_NUM_WSEQS,
};
/* DSP Queue */
#define CS40L50_DSP_QUEUE_BASE 0x11004
#define CS40L50_DSP_QUEUE_END 0x1101C
#define CS40L50_DSP_QUEUE 0x11020
#define CS40L50_PREVENT_HIBER 0x2000003
#define CS40L50_ALLOW_HIBER 0x2000004
#define CS40L50_SHUTDOWN 0x2000005
#define CS40L50_SYSTEM_RESET 0x2000007
#define CS40L50_START_I2S 0x3000002
#define CS40L50_OWT_PUSH 0x3000008
#define CS40L50_STOP_PLAYBACK 0x5000000
#define CS40L50_OWT_DELETE 0xD000000
/* Firmware files */
#define CS40L50_FW "cs40l50.wmfw"
#define CS40L50_WT "cs40l50.bin"
/* Device */
#define CS40L50_DEVID 0x0
#define CS40L50_REVID 0x4
#define CS40L50_DEVID_A 0x40A50
#define CS40L50_REVID_B0 0xB0
struct cs40l50 {
struct device *dev;
struct regmap *regmap;
struct mutex lock;
struct cs_dsp dsp;
struct gpio_desc *reset_gpio;
struct regmap_irq_chip_data *irq_data;
const struct firmware *fw;
const struct firmware *bin;
struct cs_dsp_wseq wseqs[CS40L50_NUM_WSEQS];
int irq;
u32 devid;
u32 revid;
};
int cs40l50_dsp_write(struct device *dev, struct regmap *regmap, u32 val);
int cs40l50_probe(struct cs40l50 *cs40l50);
int cs40l50_remove(struct cs40l50 *cs40l50);
extern const struct regmap_config cs40l50_regmap;
extern const struct dev_pm_ops cs40l50_pm_ops;
#endif /* __MFD_CS40L50_H__ */
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