Commit cbd69e7a authored by Jerome Brunet's avatar Jerome Brunet Committed by Greg Kroah-Hartman

clk: meson: axg: spread spectrum is on mpll2

[ Upstream commit dc4e62d3 ]

After testing, it appears that the SSEN bit controls the spread
spectrum function on MPLL2, not MPLL0.

Fixes: 78b4af31 ("clk: meson-axg: add clock controller drivers")
Signed-off-by: default avatarJerome Brunet <jbrunet@baylibre.com>
Signed-off-by: default avatarSasha Levin <sashal@kernel.org>
parent 3dffd748
......@@ -461,11 +461,6 @@ static struct clk_regmap axg_mpll0_div = {
.shift = 16,
.width = 9,
},
.ssen = {
.reg_off = HHI_MPLL_CNTL,
.shift = 25,
.width = 1,
},
.misc = {
.reg_off = HHI_PLL_TOP_MISC,
.shift = 0,
......@@ -560,6 +555,11 @@ static struct clk_regmap axg_mpll2_div = {
.shift = 16,
.width = 9,
},
.ssen = {
.reg_off = HHI_MPLL_CNTL,
.shift = 25,
.width = 1,
},
.misc = {
.reg_off = HHI_PLL_TOP_MISC,
.shift = 2,
......
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