Commit cc61c1fe authored by Ralf Baechle's avatar Ralf Baechle

MIPS R2 instruction hazard handling.

Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent bbc7f22f
......@@ -529,6 +529,7 @@ static void r4k_flush_icache_range(unsigned long __user start,
args.end = end;
on_each_cpu(local_r4k_flush_icache_range, &args, 1, 1);
instruction_hazard();
}
/*
......
......@@ -228,6 +228,22 @@ __asm__(
#endif
#if defined(CONFIG_CPU_MIPS32_R2) || defined (CONFIG_CPU_MIPS64_R2)
#define instruction_hazard() \
do { \
__label__ __next; \
__asm__ __volatile__( \
" jr.hb %0 \n" \
: \
: "r" (&&__next)); \
__next: \
; \
} while (0)
#else
#define instruction_hazard() do { } while (0)
#endif
#endif /* __ASSEMBLY__ */
#endif /* _ASM_HAZARDS_H */
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment