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Commit cce8ccca authored by Mauro Carvalho Chehab's avatar Mauro Carvalho Chehab
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media: use the BIT() macro 

As warned by cppcheck:

	[drivers/media/dvb-frontends/cx24123.c:434]: (error) Shifting signed 32-bit value by 31 bits is undefined behaviour
	[drivers/media/pci/bt8xx/bttv-input.c:87]: (error) Shifting signed 32-bit value by 31 bits is undefined behaviour
	[drivers/media/pci/bt8xx/bttv-input.c:98]: (error) Shifting signed 32-bit value by 31 bits is undefined behaviour
			...
	[drivers/media/v4l2-core/v4l2-ioctl.c:1391]: (error) Shifting signed 32-bit value by 31 bits is undefined behaviour

There are lots of places where we're doing 1 << 31. That's bad,
as, depending on the architecture, this has an undefined behavior.

The BIT() macro is already prepared to handle this, so, let's
just switch all "1 << number" macros by BIT(number) at the header files
with has 1 << 31.

Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> # exynos4-is and s3c-camif
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> # omap3isp, vsp1, xilinx, wl128x and ipu3
Reviewed-by: Benoit Parrot <bparrot@ti.com> # am437x and ti-vpe
Signed-off-by: default avatarMauro Carvalho Chehab <mchehab+samsung@kernel.org>
parent 093347ab
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Showing with 1014 additions and 1002 deletions
drivers/media/pci/cobalt/cobalt-driver.h
View file @ cce8ccca
...@@ -11,6 +11,7 @@ ...@@ -11,6 +11,7 @@
#ifndef COBALT_DRIVER_H #ifndef COBALT_DRIVER_H
#define COBALT_DRIVER_H #define COBALT_DRIVER_H
#include <linux/bitops.h>
#include <linux/module.h> #include <linux/module.h>
#include <linux/pci.h> #include <linux/pci.h>
#include <linux/spinlock.h> #include <linux/spinlock.h>
...@@ -61,37 +62,37 @@ ...@@ -61,37 +62,37 @@
#define COBALT_CLK 50000000 #define COBALT_CLK 50000000
/* System status register */ /* System status register */
#define COBALT_SYSSTAT_DIP0_MSK (1 << 0) #define COBALT_SYSSTAT_DIP0_MSK BIT(0)
#define COBALT_SYSSTAT_DIP1_MSK (1 << 1) #define COBALT_SYSSTAT_DIP1_MSK BIT(1)
#define COBALT_SYSSTAT_HSMA_PRSNTN_MSK (1 << 2) #define COBALT_SYSSTAT_HSMA_PRSNTN_MSK BIT(2)
#define COBALT_SYSSTAT_FLASH_RDYBSYN_MSK (1 << 3) #define COBALT_SYSSTAT_FLASH_RDYBSYN_MSK BIT(3)
#define COBALT_SYSSTAT_VI0_5V_MSK (1 << 4) #define COBALT_SYSSTAT_VI0_5V_MSK BIT(4)
#define COBALT_SYSSTAT_VI0_INT1_MSK (1 << 5) #define COBALT_SYSSTAT_VI0_INT1_MSK BIT(5)
#define COBALT_SYSSTAT_VI0_INT2_MSK (1 << 6) #define COBALT_SYSSTAT_VI0_INT2_MSK BIT(6)
#define COBALT_SYSSTAT_VI0_LOST_DATA_MSK (1 << 7) #define COBALT_SYSSTAT_VI0_LOST_DATA_MSK BIT(7)
#define COBALT_SYSSTAT_VI1_5V_MSK (1 << 8) #define COBALT_SYSSTAT_VI1_5V_MSK BIT(8)
#define COBALT_SYSSTAT_VI1_INT1_MSK (1 << 9) #define COBALT_SYSSTAT_VI1_INT1_MSK BIT(9)
#define COBALT_SYSSTAT_VI1_INT2_MSK (1 << 10) #define COBALT_SYSSTAT_VI1_INT2_MSK BIT(10)
#define COBALT_SYSSTAT_VI1_LOST_DATA_MSK (1 << 11) #define COBALT_SYSSTAT_VI1_LOST_DATA_MSK BIT(11)
#define COBALT_SYSSTAT_VI2_5V_MSK (1 << 12) #define COBALT_SYSSTAT_VI2_5V_MSK BIT(12)
#define COBALT_SYSSTAT_VI2_INT1_MSK (1 << 13) #define COBALT_SYSSTAT_VI2_INT1_MSK BIT(13)
#define COBALT_SYSSTAT_VI2_INT2_MSK (1 << 14) #define COBALT_SYSSTAT_VI2_INT2_MSK BIT(14)
#define COBALT_SYSSTAT_VI2_LOST_DATA_MSK (1 << 15) #define COBALT_SYSSTAT_VI2_LOST_DATA_MSK BIT(15)
#define COBALT_SYSSTAT_VI3_5V_MSK (1 << 16) #define COBALT_SYSSTAT_VI3_5V_MSK BIT(16)
#define COBALT_SYSSTAT_VI3_INT1_MSK (1 << 17) #define COBALT_SYSSTAT_VI3_INT1_MSK BIT(17)
#define COBALT_SYSSTAT_VI3_INT2_MSK (1 << 18) #define COBALT_SYSSTAT_VI3_INT2_MSK BIT(18)
#define COBALT_SYSSTAT_VI3_LOST_DATA_MSK (1 << 19) #define COBALT_SYSSTAT_VI3_LOST_DATA_MSK BIT(19)
#define COBALT_SYSSTAT_VIHSMA_5V_MSK (1 << 20) #define COBALT_SYSSTAT_VIHSMA_5V_MSK BIT(20)
#define COBALT_SYSSTAT_VIHSMA_INT1_MSK (1 << 21) #define COBALT_SYSSTAT_VIHSMA_INT1_MSK BIT(21)
#define COBALT_SYSSTAT_VIHSMA_INT2_MSK (1 << 22) #define COBALT_SYSSTAT_VIHSMA_INT2_MSK BIT(22)
#define COBALT_SYSSTAT_VIHSMA_LOST_DATA_MSK (1 << 23) #define COBALT_SYSSTAT_VIHSMA_LOST_DATA_MSK BIT(23)
#define COBALT_SYSSTAT_VOHSMA_INT1_MSK (1 << 24) #define COBALT_SYSSTAT_VOHSMA_INT1_MSK BIT(24)
#define COBALT_SYSSTAT_VOHSMA_PLL_LOCKED_MSK (1 << 25) #define COBALT_SYSSTAT_VOHSMA_PLL_LOCKED_MSK BIT(25)
#define COBALT_SYSSTAT_VOHSMA_LOST_DATA_MSK (1 << 26) #define COBALT_SYSSTAT_VOHSMA_LOST_DATA_MSK BIT(26)
#define COBALT_SYSSTAT_AUD_PLL_LOCKED_MSK (1 << 28) #define COBALT_SYSSTAT_AUD_PLL_LOCKED_MSK BIT(28)
#define COBALT_SYSSTAT_AUD_IN_LOST_DATA_MSK (1 << 29) #define COBALT_SYSSTAT_AUD_IN_LOST_DATA_MSK BIT(29)
#define COBALT_SYSSTAT_AUD_OUT_LOST_DATA_MSK (1 << 30) #define COBALT_SYSSTAT_AUD_OUT_LOST_DATA_MSK BIT(30)
#define COBALT_SYSSTAT_PCIE_SMBCLK_MSK (1 << 31) #define COBALT_SYSSTAT_PCIE_SMBCLK_MSK BIT(31)
/* Cobalt memory map */ /* Cobalt memory map */
#define COBALT_I2C_0_BASE 0x0 #define COBALT_I2C_0_BASE 0x0
......
drivers/media/pci/ivtv/ivtv-irq.h
View file @ cce8ccca
...@@ -10,20 +10,20 @@ ...@@ -10,20 +10,20 @@
#ifndef IVTV_IRQ_H #ifndef IVTV_IRQ_H
#define IVTV_IRQ_H #define IVTV_IRQ_H
#define IVTV_IRQ_ENC_START_CAP (0x1 << 31) #define IVTV_IRQ_ENC_START_CAP BIT(31)
#define IVTV_IRQ_ENC_EOS (0x1 << 30) #define IVTV_IRQ_ENC_EOS BIT(30)
#define IVTV_IRQ_ENC_VBI_CAP (0x1 << 29) #define IVTV_IRQ_ENC_VBI_CAP BIT(29)
#define IVTV_IRQ_ENC_VIM_RST (0x1 << 28) #define IVTV_IRQ_ENC_VIM_RST BIT(28)
#define IVTV_IRQ_ENC_DMA_COMPLETE (0x1 << 27) #define IVTV_IRQ_ENC_DMA_COMPLETE BIT(27)
#define IVTV_IRQ_ENC_PIO_COMPLETE (0x1 << 25) #define IVTV_IRQ_ENC_PIO_COMPLETE BIT(25)
#define IVTV_IRQ_DEC_AUD_MODE_CHG (0x1 << 24) #define IVTV_IRQ_DEC_AUD_MODE_CHG BIT(24)
#define IVTV_IRQ_DEC_DATA_REQ (0x1 << 22) #define IVTV_IRQ_DEC_DATA_REQ BIT(22)
#define IVTV_IRQ_DEC_DMA_COMPLETE (0x1 << 20) #define IVTV_IRQ_DEC_DMA_COMPLETE BIT(20)
#define IVTV_IRQ_DEC_VBI_RE_INSERT (0x1 << 19) #define IVTV_IRQ_DEC_VBI_RE_INSERT BIT(19)
#define IVTV_IRQ_DMA_ERR (0x1 << 18) #define IVTV_IRQ_DMA_ERR BIT(18)
#define IVTV_IRQ_DMA_WRITE (0x1 << 17) #define IVTV_IRQ_DMA_WRITE BIT(17)
#define IVTV_IRQ_DMA_READ (0x1 << 16) #define IVTV_IRQ_DMA_READ BIT(16)
#define IVTV_IRQ_DEC_VSYNC (0x1 << 10) #define IVTV_IRQ_DEC_VSYNC BIT(10)
/* IRQ Masks */ /* IRQ Masks */
#define IVTV_IRQ_MASK_INIT (IVTV_IRQ_DMA_ERR|IVTV_IRQ_ENC_DMA_COMPLETE|\ #define IVTV_IRQ_MASK_INIT (IVTV_IRQ_DMA_ERR|IVTV_IRQ_ENC_DMA_COMPLETE|\
......
drivers/media/pci/mantis/mantis_reg.h
View file @ cce8ccca
...@@ -14,44 +14,44 @@ ...@@ -14,44 +14,44 @@
#define MANTIS_INT_MASK 0x04 #define MANTIS_INT_MASK 0x04
#define MANTIS_INT_RISCSTAT (0x0f << 28) #define MANTIS_INT_RISCSTAT (0x0f << 28)
#define MANTIS_INT_RISCEN (0x01 << 27) #define MANTIS_INT_RISCEN BIT(27)
#define MANTIS_INT_I2CRACK (0x01 << 26) #define MANTIS_INT_I2CRACK BIT(26)
/* #define MANTIS_INT_GPIF (0xff << 12) */ /* #define MANTIS_INT_GPIF (0xff << 12) */
#define MANTIS_INT_PCMCIA7 (0x01 << 19) #define MANTIS_INT_PCMCIA7 BIT(19)
#define MANTIS_INT_PCMCIA6 (0x01 << 18) #define MANTIS_INT_PCMCIA6 BIT(18)
#define MANTIS_INT_PCMCIA5 (0x01 << 17) #define MANTIS_INT_PCMCIA5 BIT(17)
#define MANTIS_INT_PCMCIA4 (0x01 << 16) #define MANTIS_INT_PCMCIA4 BIT(16)
#define MANTIS_INT_PCMCIA3 (0x01 << 15) #define MANTIS_INT_PCMCIA3 BIT(15)
#define MANTIS_INT_PCMCIA2 (0x01 << 14) #define MANTIS_INT_PCMCIA2 BIT(14)
#define MANTIS_INT_PCMCIA1 (0x01 << 13) #define MANTIS_INT_PCMCIA1 BIT(13)
#define MANTIS_INT_PCMCIA0 (0x01 << 12) #define MANTIS_INT_PCMCIA0 BIT(12)
#define MANTIS_INT_IRQ1 (0x01 << 11) #define MANTIS_INT_IRQ1 BIT(11)
#define MANTIS_INT_IRQ0 (0x01 << 10) #define MANTIS_INT_IRQ0 BIT(10)
#define MANTIS_INT_OCERR (0x01 << 8) #define MANTIS_INT_OCERR BIT(8)
#define MANTIS_INT_PABORT (0x01 << 7) #define MANTIS_INT_PABORT BIT(7)
#define MANTIS_INT_RIPERR (0x01 << 6) #define MANTIS_INT_RIPERR BIT(6)
#define MANTIS_INT_PPERR (0x01 << 5) #define MANTIS_INT_PPERR BIT(5)
#define MANTIS_INT_FTRGT (0x01 << 3) #define MANTIS_INT_FTRGT BIT(3)
#define MANTIS_INT_RISCI (0x01 << 1) #define MANTIS_INT_RISCI BIT(1)
#define MANTIS_INT_I2CDONE (0x01 << 0) #define MANTIS_INT_I2CDONE BIT(0)
/* DMA */ /* DMA */
#define MANTIS_DMA_CTL 0x08 #define MANTIS_DMA_CTL 0x08
#define MANTIS_GPIF_RD (0xff << 24) #define MANTIS_GPIF_RD (0xff << 24)
#define MANTIS_GPIF_WR (0xff << 16) #define MANTIS_GPIF_WR (0xff << 16)
#define MANTIS_CPU_DO (0x01 << 10) #define MANTIS_CPU_DO BIT(10)
#define MANTIS_DRV_DO (0x01 << 9) #define MANTIS_DRV_DO BIT(9)
#define MANTIS_I2C_RD (0x01 << 7) #define MANTIS_I2C_RD BIT(7)
#define MANTIS_I2C_WR (0x01 << 6) #define MANTIS_I2C_WR BIT(6)
#define MANTIS_DCAP_MODE (0x01 << 5) #define MANTIS_DCAP_MODE BIT(5)
#define MANTIS_FIFO_TP_4 (0x00 << 3) #define MANTIS_FIFO_TP_4 (0x00 << 3)
#define MANTIS_FIFO_TP_8 (0x01 << 3) #define MANTIS_FIFO_TP_8 (0x01 << 3)
#define MANTIS_FIFO_TP_16 (0x02 << 3) #define MANTIS_FIFO_TP_16 (0x02 << 3)
#define MANTIS_FIFO_EN (0x01 << 2) #define MANTIS_FIFO_EN BIT(2)
#define MANTIS_DCAP_EN (0x01 << 1) #define MANTIS_DCAP_EN BIT(1)
#define MANTIS_RISC_EN (0x01 << 0) #define MANTIS_RISC_EN BIT(0)
/* DEBUG */ /* DEBUG */
#define MANTIS_DEBUGREG 0x0c #define MANTIS_DEBUGREG 0x0c
...@@ -68,8 +68,8 @@ ...@@ -68,8 +68,8 @@
#define MANTIS_I2C_RATE_2 (0x01 << 6) #define MANTIS_I2C_RATE_2 (0x01 << 6)
#define MANTIS_I2C_RATE_3 (0x02 << 6) #define MANTIS_I2C_RATE_3 (0x02 << 6)
#define MANTIS_I2C_RATE_4 (0x03 << 6) #define MANTIS_I2C_RATE_4 (0x03 << 6)
#define MANTIS_I2C_STOP (0x01 << 5) #define MANTIS_I2C_STOP BIT(5)
#define MANTIS_I2C_PGMODE (0x01 << 3) #define MANTIS_I2C_PGMODE BIT(3)
/* DATA */ /* DATA */
#define MANTIS_CMD_DATA_R1 0x20 #define MANTIS_CMD_DATA_R1 0x20
...@@ -85,77 +85,77 @@ ...@@ -85,77 +85,77 @@
#define MANTIS_CMD_DATA_4 (0xff << 0) #define MANTIS_CMD_DATA_4 (0xff << 0)
#define MANTIS_CONTROL 0x28 #define MANTIS_CONTROL 0x28
#define MANTIS_DET (0x01 << 7) #define MANTIS_DET BIT(7)
#define MANTIS_DAT_CF_EN (0x01 << 6) #define MANTIS_DAT_CF_EN BIT(6)
#define MANTIS_ACS (0x03 << 4) #define MANTIS_ACS (0x03 << 4)
#define MANTIS_VCCEN (0x01 << 3) #define MANTIS_VCCEN BIT(3)
#define MANTIS_BYPASS (0x01 << 2) #define MANTIS_BYPASS BIT(2)
#define MANTIS_MRST (0x01 << 1) #define MANTIS_MRST BIT(1)
#define MANTIS_CRST_INT (0x01 << 0) #define MANTIS_CRST_INT BIT(0)
#define MANTIS_GPIF_CFGSLA 0x84 #define MANTIS_GPIF_CFGSLA 0x84
#define MANTIS_GPIF_WAITSMPL (0x07 << 28) #define MANTIS_GPIF_WAITSMPL (0x07 << 28)
#define MANTIS_GPIF_BYTEADDRSUB (0x01 << 25) #define MANTIS_GPIF_BYTEADDRSUB BIT(25)
#define MANTIS_GPIF_WAITPOL (0x01 << 24) #define MANTIS_GPIF_WAITPOL BIT(24)
#define MANTIS_GPIF_NCDELAY (0x07 << 20) #define MANTIS_GPIF_NCDELAY (0x07 << 20)
#define MANTIS_GPIF_RW2CSDELAY (0x07 << 16) #define MANTIS_GPIF_RW2CSDELAY (0x07 << 16)
#define MANTIS_GPIF_SLFTIMEDMODE (0x01 << 15) #define MANTIS_GPIF_SLFTIMEDMODE BIT(15)
#define MANTIS_GPIF_SLFTIMEDDELY (0x7f << 8) #define MANTIS_GPIF_SLFTIMEDDELY (0x7f << 8)
#define MANTIS_GPIF_DEVTYPE (0x07 << 4) #define MANTIS_GPIF_DEVTYPE (0x07 << 4)
#define MANTIS_GPIF_BIGENDIAN (0x01 << 3) #define MANTIS_GPIF_BIGENDIAN BIT(3)
#define MANTIS_GPIF_FETCHCMD (0x03 << 1) #define MANTIS_GPIF_FETCHCMD (0x03 << 1)
#define MANTIS_GPIF_HWORDDEV (0x01 << 0) #define MANTIS_GPIF_HWORDDEV BIT(0)
#define MANTIS_GPIF_WSTOPER 0x90 #define MANTIS_GPIF_WSTOPER 0x90
#define MANTIS_GPIF_WSTOPERWREN3 (0x01 << 31) #define MANTIS_GPIF_WSTOPERWREN3 BIT(31)
#define MANTIS_GPIF_PARBOOTN (0x01 << 29) #define MANTIS_GPIF_PARBOOTN BIT(29)
#define MANTIS_GPIF_WSTOPERSLID3 (0x1f << 24) #define MANTIS_GPIF_WSTOPERSLID3 (0x1f << 24)
#define MANTIS_GPIF_WSTOPERWREN2 (0x01 << 23) #define MANTIS_GPIF_WSTOPERWREN2 BIT(23)
#define MANTIS_GPIF_WSTOPERSLID2 (0x1f << 16) #define MANTIS_GPIF_WSTOPERSLID2 (0x1f << 16)
#define MANTIS_GPIF_WSTOPERWREN1 (0x01 << 15) #define MANTIS_GPIF_WSTOPERWREN1 BIT(15)
#define MANTIS_GPIF_WSTOPERSLID1 (0x1f << 8) #define MANTIS_GPIF_WSTOPERSLID1 (0x1f << 8)
#define MANTIS_GPIF_WSTOPERWREN0 (0x01 << 7) #define MANTIS_GPIF_WSTOPERWREN0 BIT(7)
#define MANTIS_GPIF_WSTOPERSLID0 (0x1f << 0) #define MANTIS_GPIF_WSTOPERSLID0 (0x1f << 0)
#define MANTIS_GPIF_CS2RW 0x94 #define MANTIS_GPIF_CS2RW 0x94
#define MANTIS_GPIF_CS2RWWREN3 (0x01 << 31) #define MANTIS_GPIF_CS2RWWREN3 BIT(31)
#define MANTIS_GPIF_CS2RWDELY3 (0x3f << 24) #define MANTIS_GPIF_CS2RWDELY3 (0x3f << 24)
#define MANTIS_GPIF_CS2RWWREN2 (0x01 << 23) #define MANTIS_GPIF_CS2RWWREN2 BIT(23)
#define MANTIS_GPIF_CS2RWDELY2 (0x3f << 16) #define MANTIS_GPIF_CS2RWDELY2 (0x3f << 16)
#define MANTIS_GPIF_CS2RWWREN1 (0x01 << 15) #define MANTIS_GPIF_CS2RWWREN1 BIT(15)
#define MANTIS_GPIF_CS2RWDELY1 (0x3f << 8) #define MANTIS_GPIF_CS2RWDELY1 (0x3f << 8)
#define MANTIS_GPIF_CS2RWWREN0 (0x01 << 7) #define MANTIS_GPIF_CS2RWWREN0 BIT(7)
#define MANTIS_GPIF_CS2RWDELY0 (0x3f << 0) #define MANTIS_GPIF_CS2RWDELY0 (0x3f << 0)
#define MANTIS_GPIF_IRQCFG 0x98 #define MANTIS_GPIF_IRQCFG 0x98
#define MANTIS_GPIF_IRQPOL (0x01 << 8) #define MANTIS_GPIF_IRQPOL BIT(8)
#define MANTIS_MASK_WRACK (0x01 << 7) #define MANTIS_MASK_WRACK BIT(7)
#define MANTIS_MASK_BRRDY (0x01 << 6) #define MANTIS_MASK_BRRDY BIT(6)
#define MANTIS_MASK_OVFLW (0x01 << 5) #define MANTIS_MASK_OVFLW BIT(5)
#define MANTIS_MASK_OTHERR (0x01 << 4) #define MANTIS_MASK_OTHERR BIT(4)
#define MANTIS_MASK_WSTO (0x01 << 3) #define MANTIS_MASK_WSTO BIT(3)
#define MANTIS_MASK_EXTIRQ (0x01 << 2) #define MANTIS_MASK_EXTIRQ BIT(2)
#define MANTIS_MASK_PLUGIN (0x01 << 1) #define MANTIS_MASK_PLUGIN BIT(1)
#define MANTIS_MASK_PLUGOUT (0x01 << 0) #define MANTIS_MASK_PLUGOUT BIT(0)
#define MANTIS_GPIF_STATUS 0x9c #define MANTIS_GPIF_STATUS 0x9c
#define MANTIS_SBUF_KILLOP (0x01 << 15) #define MANTIS_SBUF_KILLOP BIT(15)
#define MANTIS_SBUF_OPDONE (0x01 << 14) #define MANTIS_SBUF_OPDONE BIT(14)
#define MANTIS_SBUF_EMPTY (0x01 << 13) #define MANTIS_SBUF_EMPTY BIT(13)
#define MANTIS_GPIF_DETSTAT (0x01 << 9) #define MANTIS_GPIF_DETSTAT BIT(9)
#define MANTIS_GPIF_INTSTAT (0x01 << 8) #define MANTIS_GPIF_INTSTAT BIT(8)
#define MANTIS_GPIF_WRACK (0x01 << 7) #define MANTIS_GPIF_WRACK BIT(7)
#define MANTIS_GPIF_BRRDY (0x01 << 6) #define MANTIS_GPIF_BRRDY BIT(6)
#define MANTIS_SBUF_OVFLW (0x01 << 5) #define MANTIS_SBUF_OVFLW BIT(5)
#define MANTIS_GPIF_OTHERR (0x01 << 4) #define MANTIS_GPIF_OTHERR BIT(4)
#define MANTIS_SBUF_WSTO (0x01 << 3) #define MANTIS_SBUF_WSTO BIT(3)
#define MANTIS_GPIF_EXTIRQ (0x01 << 2) #define MANTIS_GPIF_EXTIRQ BIT(2)
#define MANTIS_CARD_PLUGIN (0x01 << 1) #define MANTIS_CARD_PLUGIN BIT(1)
#define MANTIS_CARD_PLUGOUT (0x01 << 0) #define MANTIS_CARD_PLUGOUT BIT(0)
#define MANTIS_GPIF_BRADDR 0xa0 #define MANTIS_GPIF_BRADDR 0xa0
#define MANTIS_GPIF_PCMCIAREG (0x01 << 27) #define MANTIS_GPIF_PCMCIAREG BIT(27)
#define MANTIS_GPIF_PCMCIAIOM (0x01 << 26) #define MANTIS_GPIF_PCMCIAIOM BIT(26)
#define MANTIS_GPIF_BR_ADDR (0xfffffff << 0) #define MANTIS_GPIF_BR_ADDR (0xfffffff << 0)
#define MANTIS_GPIF_BRBYTES 0xa4 #define MANTIS_GPIF_BRBYTES 0xa4
...@@ -167,9 +167,9 @@ ...@@ -167,9 +167,9 @@
#define MANTIS_CARD_RESET 0xac #define MANTIS_CARD_RESET 0xac
#define MANTIS_GPIF_ADDR 0xb0 #define MANTIS_GPIF_ADDR 0xb0
#define MANTIS_GPIF_HIFRDWRN (0x01 << 31) #define MANTIS_GPIF_HIFRDWRN BIT(31)
#define MANTIS_GPIF_PCMCIAREG (0x01 << 27) #define MANTIS_GPIF_PCMCIAREG BIT(27)
#define MANTIS_GPIF_PCMCIAIOM (0x01 << 26) #define MANTIS_GPIF_PCMCIAIOM BIT(26)
#define MANTIS_GPIF_HIFADDR (0xfffffff << 0) #define MANTIS_GPIF_HIFADDR (0xfffffff << 0)
#define MANTIS_GPIF_DOUT 0xb4 #define MANTIS_GPIF_DOUT 0xb4
......
drivers/media/pci/solo6x10/solo6x10-regs.h
View file @ cce8ccca
This diff is collapsed.
drivers/media/platform/am437x/am437x-vpfe_regs.h
View file @ cce8ccca
...@@ -66,13 +66,13 @@ ...@@ -66,13 +66,13 @@
#define VPFE_PIX_FMT_MASK 3 #define VPFE_PIX_FMT_MASK 3
#define VPFE_PIX_FMT_SHIFT 12 #define VPFE_PIX_FMT_SHIFT 12
#define VPFE_VP2SDR_DISABLE 0xfffbffff #define VPFE_VP2SDR_DISABLE 0xfffbffff
#define VPFE_WEN_ENABLE (1 << 17) #define VPFE_WEN_ENABLE BIT(17)
#define VPFE_SDR2RSZ_DISABLE 0xfff7ffff #define VPFE_SDR2RSZ_DISABLE 0xfff7ffff
#define VPFE_VDHDEN_ENABLE (1 << 16) #define VPFE_VDHDEN_ENABLE BIT(16)
#define VPFE_LPF_ENABLE (1 << 14) #define VPFE_LPF_ENABLE BIT(14)
#define VPFE_ALAW_ENABLE (1 << 3) #define VPFE_ALAW_ENABLE BIT(3)
#define VPFE_ALAW_GAMMA_WD_MASK 7 #define VPFE_ALAW_GAMMA_WD_MASK 7
#define VPFE_BLK_CLAMP_ENABLE (1 << 31) #define VPFE_BLK_CLAMP_ENABLE BIT(31)
#define VPFE_BLK_SGAIN_MASK 0x1f #define VPFE_BLK_SGAIN_MASK 0x1f
#define VPFE_BLK_ST_PXL_MASK 0x7fff #define VPFE_BLK_ST_PXL_MASK 0x7fff
#define VPFE_BLK_ST_PXL_SHIFT 10 #define VPFE_BLK_ST_PXL_SHIFT 10
...@@ -85,8 +85,8 @@ ...@@ -85,8 +85,8 @@
#define VPFE_BLK_COMP_GB_COMP_SHIFT 8 #define VPFE_BLK_COMP_GB_COMP_SHIFT 8
#define VPFE_BLK_COMP_GR_COMP_SHIFT 16 #define VPFE_BLK_COMP_GR_COMP_SHIFT 16
#define VPFE_BLK_COMP_R_COMP_SHIFT 24 #define VPFE_BLK_COMP_R_COMP_SHIFT 24
#define VPFE_LATCH_ON_VSYNC_DISABLE (1 << 15) #define VPFE_LATCH_ON_VSYNC_DISABLE BIT(15)
#define VPFE_DATA_PACK_ENABLE (1 << 11) #define VPFE_DATA_PACK_ENABLE BIT(11)
#define VPFE_HORZ_INFO_SPH_SHIFT 16 #define VPFE_HORZ_INFO_SPH_SHIFT 16
#define VPFE_VERT_START_SLV0_SHIFT 16 #define VPFE_VERT_START_SLV0_SHIFT 16
#define VPFE_VDINT_VDINT0_SHIFT 16 #define VPFE_VDINT_VDINT0_SHIFT 16
...@@ -114,15 +114,15 @@ ...@@ -114,15 +114,15 @@
#define VPFE_SYN_FLDMODE_MASK 1 #define VPFE_SYN_FLDMODE_MASK 1
#define VPFE_SYN_FLDMODE_SHIFT 7 #define VPFE_SYN_FLDMODE_SHIFT 7
#define VPFE_REC656IF_BT656_EN 3 #define VPFE_REC656IF_BT656_EN 3
#define VPFE_SYN_MODE_VD_POL_NEGATIVE (1 << 2) #define VPFE_SYN_MODE_VD_POL_NEGATIVE BIT(2)
#define VPFE_CCDCFG_Y8POS_SHIFT 11 #define VPFE_CCDCFG_Y8POS_SHIFT 11
#define VPFE_CCDCFG_BW656_10BIT (1 << 5) #define VPFE_CCDCFG_BW656_10BIT BIT(5)
#define VPFE_SDOFST_FIELD_INTERLEAVED 0x249 #define VPFE_SDOFST_FIELD_INTERLEAVED 0x249
#define VPFE_NO_CULLING 0xffff00ff #define VPFE_NO_CULLING 0xffff00ff
#define VPFE_VDINT0 (1 << 0) #define VPFE_VDINT0 BIT(0)
#define VPFE_VDINT1 (1 << 1) #define VPFE_VDINT1 BIT(1)
#define VPFE_VDINT2 (1 << 2) #define VPFE_VDINT2 BIT(2)
#define VPFE_DMA_CNTL_OVERFLOW (1 << 31) #define VPFE_DMA_CNTL_OVERFLOW BIT(31)
#define VPFE_CONFIG_PCLK_INV_SHIFT 0 #define VPFE_CONFIG_PCLK_INV_SHIFT 0
#define VPFE_CONFIG_PCLK_INV_MASK 1 #define VPFE_CONFIG_PCLK_INV_MASK 1
......
drivers/media/platform/davinci/dm644x_ccdc_regs.h
View file @ cce8ccca
...@@ -66,13 +66,13 @@ ...@@ -66,13 +66,13 @@
#define CCDC_PIX_FMT_MASK 3 #define CCDC_PIX_FMT_MASK 3
#define CCDC_PIX_FMT_SHIFT 12 #define CCDC_PIX_FMT_SHIFT 12
#define CCDC_VP2SDR_DISABLE 0xFFFBFFFF #define CCDC_VP2SDR_DISABLE 0xFFFBFFFF
#define CCDC_WEN_ENABLE (1 << 17) #define CCDC_WEN_ENABLE BIT(17)
#define CCDC_SDR2RSZ_DISABLE 0xFFF7FFFF #define CCDC_SDR2RSZ_DISABLE 0xFFF7FFFF
#define CCDC_VDHDEN_ENABLE (1 << 16) #define CCDC_VDHDEN_ENABLE BIT(16)
#define CCDC_LPF_ENABLE (1 << 14) #define CCDC_LPF_ENABLE BIT(14)
#define CCDC_ALAW_ENABLE (1 << 3) #define CCDC_ALAW_ENABLE BIT(3)
#define CCDC_ALAW_GAMMA_WD_MASK 7 #define CCDC_ALAW_GAMMA_WD_MASK 7
#define CCDC_BLK_CLAMP_ENABLE (1 << 31) #define CCDC_BLK_CLAMP_ENABLE BIT(31)
#define CCDC_BLK_SGAIN_MASK 0x1F #define CCDC_BLK_SGAIN_MASK 0x1F
#define CCDC_BLK_ST_PXL_MASK 0x7FFF #define CCDC_BLK_ST_PXL_MASK 0x7FFF
#define CCDC_BLK_ST_PXL_SHIFT 10 #define CCDC_BLK_ST_PXL_SHIFT 10
...@@ -85,11 +85,11 @@ ...@@ -85,11 +85,11 @@
#define CCDC_BLK_COMP_GB_COMP_SHIFT 8 #define CCDC_BLK_COMP_GB_COMP_SHIFT 8
#define CCDC_BLK_COMP_GR_COMP_SHIFT 16 #define CCDC_BLK_COMP_GR_COMP_SHIFT 16
#define CCDC_BLK_COMP_R_COMP_SHIFT 24 #define CCDC_BLK_COMP_R_COMP_SHIFT 24
#define CCDC_LATCH_ON_VSYNC_DISABLE (1 << 15) #define CCDC_LATCH_ON_VSYNC_DISABLE BIT(15)
#define CCDC_FPC_ENABLE (1 << 15) #define CCDC_FPC_ENABLE BIT(15)
#define CCDC_FPC_DISABLE 0 #define CCDC_FPC_DISABLE 0
#define CCDC_FPC_FPC_NUM_MASK 0x7FFF #define CCDC_FPC_FPC_NUM_MASK 0x7FFF
#define CCDC_DATA_PACK_ENABLE (1 << 11) #define CCDC_DATA_PACK_ENABLE BIT(11)
#define CCDC_FMTCFG_VPIN_MASK 7 #define CCDC_FMTCFG_VPIN_MASK 7
#define CCDC_FMTCFG_VPIN_SHIFT 12 #define CCDC_FMTCFG_VPIN_SHIFT 12
#define CCDC_FMT_HORZ_FMTLNH_MASK 0x1FFF #define CCDC_FMT_HORZ_FMTLNH_MASK 0x1FFF
...@@ -132,9 +132,9 @@ ...@@ -132,9 +132,9 @@
#define CCDC_SYN_FLDMODE_MASK 1 #define CCDC_SYN_FLDMODE_MASK 1
#define CCDC_SYN_FLDMODE_SHIFT 7 #define CCDC_SYN_FLDMODE_SHIFT 7
#define CCDC_REC656IF_BT656_EN 3 #define CCDC_REC656IF_BT656_EN 3
#define CCDC_SYN_MODE_VD_POL_NEGATIVE (1 << 2) #define CCDC_SYN_MODE_VD_POL_NEGATIVE BIT(2)
#define CCDC_CCDCFG_Y8POS_SHIFT 11 #define CCDC_CCDCFG_Y8POS_SHIFT 11
#define CCDC_CCDCFG_BW656_10BIT (1 << 5) #define CCDC_CCDCFG_BW656_10BIT BIT(5)
#define CCDC_SDOFST_FIELD_INTERLEAVED 0x249 #define CCDC_SDOFST_FIELD_INTERLEAVED 0x249
#define CCDC_NO_CULLING 0xffff00ff #define CCDC_NO_CULLING 0xffff00ff
#endif #endif
drivers/media/platform/exynos4-is/fimc-lite-reg.h
View file @ cce8ccca
...@@ -6,6 +6,8 @@ ...@@ -6,6 +6,8 @@
#ifndef FIMC_LITE_REG_H_ #ifndef FIMC_LITE_REG_H_
#define FIMC_LITE_REG_H_ #define FIMC_LITE_REG_H_
#include <linux/bitops.h>
#include "fimc-lite.h" #include "fimc-lite.h"
/* Camera Source size */ /* Camera Source size */
...@@ -27,27 +29,27 @@ ...@@ -27,27 +29,27 @@
/* User defined formats. x = 0...15 */ /* User defined formats. x = 0...15 */
#define FLITE_REG_CIGCTRL_USER(x) ((0x30 + x - 1) << 24) #define FLITE_REG_CIGCTRL_USER(x) ((0x30 + x - 1) << 24)
#define FLITE_REG_CIGCTRL_FMT_MASK (0x3f << 24) #define FLITE_REG_CIGCTRL_FMT_MASK (0x3f << 24)
#define FLITE_REG_CIGCTRL_SHADOWMASK_DISABLE (1 << 21) #define FLITE_REG_CIGCTRL_SHADOWMASK_DISABLE BIT(21)
#define FLITE_REG_CIGCTRL_ODMA_DISABLE (1 << 20) #define FLITE_REG_CIGCTRL_ODMA_DISABLE BIT(20)
#define FLITE_REG_CIGCTRL_SWRST_REQ (1 << 19) #define FLITE_REG_CIGCTRL_SWRST_REQ BIT(19)
#define FLITE_REG_CIGCTRL_SWRST_RDY (1 << 18) #define FLITE_REG_CIGCTRL_SWRST_RDY BIT(18)
#define FLITE_REG_CIGCTRL_SWRST (1 << 17) #define FLITE_REG_CIGCTRL_SWRST BIT(17)
#define FLITE_REG_CIGCTRL_TEST_PATTERN_COLORBAR (1 << 15) #define FLITE_REG_CIGCTRL_TEST_PATTERN_COLORBAR BIT(15)
#define FLITE_REG_CIGCTRL_INVPOLPCLK (1 << 14) #define FLITE_REG_CIGCTRL_INVPOLPCLK BIT(14)
#define FLITE_REG_CIGCTRL_INVPOLVSYNC (1 << 13) #define FLITE_REG_CIGCTRL_INVPOLVSYNC BIT(13)
#define FLITE_REG_CIGCTRL_INVPOLHREF (1 << 12) #define FLITE_REG_CIGCTRL_INVPOLHREF BIT(12)
/* Interrupts mask bits (1 disables an interrupt) */ /* Interrupts mask bits (1 disables an interrupt) */
#define FLITE_REG_CIGCTRL_IRQ_LASTEN (1 << 8) #define FLITE_REG_CIGCTRL_IRQ_LASTEN BIT(8)
#define FLITE_REG_CIGCTRL_IRQ_ENDEN (1 << 7) #define FLITE_REG_CIGCTRL_IRQ_ENDEN BIT(7)
#define FLITE_REG_CIGCTRL_IRQ_STARTEN (1 << 6) #define FLITE_REG_CIGCTRL_IRQ_STARTEN BIT(6)
#define FLITE_REG_CIGCTRL_IRQ_OVFEN (1 << 5) #define FLITE_REG_CIGCTRL_IRQ_OVFEN BIT(5)
#define FLITE_REG_CIGCTRL_IRQ_DISABLE_MASK (0xf << 5) #define FLITE_REG_CIGCTRL_IRQ_DISABLE_MASK (0xf << 5)
#define FLITE_REG_CIGCTRL_SELCAM_MIPI (1 << 3) #define FLITE_REG_CIGCTRL_SELCAM_MIPI BIT(3)
/* Image Capture Enable */ /* Image Capture Enable */
#define FLITE_REG_CIIMGCPT 0x08 #define FLITE_REG_CIIMGCPT 0x08
#define FLITE_REG_CIIMGCPT_IMGCPTEN (1 << 31) #define FLITE_REG_CIIMGCPT_IMGCPTEN BIT(31)
#define FLITE_REG_CIIMGCPT_CPT_FREN (1 << 25) #define FLITE_REG_CIIMGCPT_CPT_FREN BIT(25)
#define FLITE_REG_CIIMGCPT_CPT_MOD_FRCNT (1 << 18) #define FLITE_REG_CIIMGCPT_CPT_MOD_FRCNT (1 << 18)
#define FLITE_REG_CIIMGCPT_CPT_MOD_FREN (0 << 18) #define FLITE_REG_CIIMGCPT_CPT_MOD_FREN (0 << 18)
...@@ -56,10 +58,10 @@ ...@@ -56,10 +58,10 @@
/* Camera Window Offset */ /* Camera Window Offset */
#define FLITE_REG_CIWDOFST 0x10 #define FLITE_REG_CIWDOFST 0x10
#define FLITE_REG_CIWDOFST_WINOFSEN (1 << 31) #define FLITE_REG_CIWDOFST_WINOFSEN BIT(31)
#define FLITE_REG_CIWDOFST_CLROVIY (1 << 31) #define FLITE_REG_CIWDOFST_CLROVIY BIT(31)
#define FLITE_REG_CIWDOFST_CLROVFICB (1 << 15) #define FLITE_REG_CIWDOFST_CLROVFICB BIT(15)
#define FLITE_REG_CIWDOFST_CLROVFICR (1 << 14) #define FLITE_REG_CIWDOFST_CLROVFICR BIT(14)
#define FLITE_REG_CIWDOFST_OFST_MASK ((0x1fff << 16) | 0x1fff) #define FLITE_REG_CIWDOFST_OFST_MASK ((0x1fff << 16) | 0x1fff)
/* Camera Window Offset2 */ /* Camera Window Offset2 */
...@@ -67,8 +69,8 @@ ...@@ -67,8 +69,8 @@
/* Camera Output DMA Format */ /* Camera Output DMA Format */
#define FLITE_REG_CIODMAFMT 0x18 #define FLITE_REG_CIODMAFMT 0x18
#define FLITE_REG_CIODMAFMT_RAW_CON (1 << 15) #define FLITE_REG_CIODMAFMT_RAW_CON BIT(15)
#define FLITE_REG_CIODMAFMT_PACK12 (1 << 14) #define FLITE_REG_CIODMAFMT_PACK12 BIT(14)
#define FLITE_REG_CIODMAFMT_YCBYCR (0 << 4) #define FLITE_REG_CIODMAFMT_YCBYCR (0 << 4)
#define FLITE_REG_CIODMAFMT_YCRYCB (1 << 4) #define FLITE_REG_CIODMAFMT_YCRYCB (1 << 4)
#define FLITE_REG_CIODMAFMT_CBYCRY (2 << 4) #define FLITE_REG_CIODMAFMT_CBYCRY (2 << 4)
...@@ -88,34 +90,34 @@ ...@@ -88,34 +90,34 @@
/* Camera Status */ /* Camera Status */
#define FLITE_REG_CISTATUS 0x40 #define FLITE_REG_CISTATUS 0x40
#define FLITE_REG_CISTATUS_MIPI_VVALID (1 << 22) #define FLITE_REG_CISTATUS_MIPI_VVALID BIT(22)
#define FLITE_REG_CISTATUS_MIPI_HVALID (1 << 21) #define FLITE_REG_CISTATUS_MIPI_HVALID BIT(21)
#define FLITE_REG_CISTATUS_MIPI_DVALID (1 << 20) #define FLITE_REG_CISTATUS_MIPI_DVALID BIT(20)
#define FLITE_REG_CISTATUS_ITU_VSYNC (1 << 14) #define FLITE_REG_CISTATUS_ITU_VSYNC BIT(14)
#define FLITE_REG_CISTATUS_ITU_HREFF (1 << 13) #define FLITE_REG_CISTATUS_ITU_HREFF BIT(13)
#define FLITE_REG_CISTATUS_OVFIY (1 << 10) #define FLITE_REG_CISTATUS_OVFIY BIT(10)
#define FLITE_REG_CISTATUS_OVFICB (1 << 9) #define FLITE_REG_CISTATUS_OVFICB BIT(9)
#define FLITE_REG_CISTATUS_OVFICR (1 << 8) #define FLITE_REG_CISTATUS_OVFICR BIT(8)
#define FLITE_REG_CISTATUS_IRQ_SRC_OVERFLOW (1 << 7) #define FLITE_REG_CISTATUS_IRQ_SRC_OVERFLOW BIT(7)
#define FLITE_REG_CISTATUS_IRQ_SRC_LASTCAPEND (1 << 6) #define FLITE_REG_CISTATUS_IRQ_SRC_LASTCAPEND BIT(6)
#define FLITE_REG_CISTATUS_IRQ_SRC_FRMSTART (1 << 5) #define FLITE_REG_CISTATUS_IRQ_SRC_FRMSTART BIT(5)
#define FLITE_REG_CISTATUS_IRQ_SRC_FRMEND (1 << 4) #define FLITE_REG_CISTATUS_IRQ_SRC_FRMEND BIT(4)
#define FLITE_REG_CISTATUS_IRQ_CAM (1 << 0) #define FLITE_REG_CISTATUS_IRQ_CAM BIT(0)
#define FLITE_REG_CISTATUS_IRQ_MASK (0xf << 4) #define FLITE_REG_CISTATUS_IRQ_MASK (0xf << 4)
/* Camera Status2 */ /* Camera Status2 */
#define FLITE_REG_CISTATUS2 0x44 #define FLITE_REG_CISTATUS2 0x44
#define FLITE_REG_CISTATUS2_LASTCAPEND (1 << 1) #define FLITE_REG_CISTATUS2_LASTCAPEND BIT(1)
#define FLITE_REG_CISTATUS2_FRMEND (1 << 0) #define FLITE_REG_CISTATUS2_FRMEND BIT(0)
/* Qos Threshold */ /* Qos Threshold */
#define FLITE_REG_CITHOLD 0xf0 #define FLITE_REG_CITHOLD 0xf0
#define FLITE_REG_CITHOLD_W_QOS_EN (1 << 30) #define FLITE_REG_CITHOLD_W_QOS_EN BIT(30)
/* Camera General Purpose */ /* Camera General Purpose */
#define FLITE_REG_CIGENERAL 0xfc #define FLITE_REG_CIGENERAL 0xfc
/* b0: 1 - camera B, 0 - camera A */ /* b0: 1 - camera B, 0 - camera A */
#define FLITE_REG_CIGENERAL_CAM_B (1 << 0) #define FLITE_REG_CIGENERAL_CAM_B BIT(0)
#define FLITE_REG_CIFCNTSEQ 0x100 #define FLITE_REG_CIFCNTSEQ 0x100
#define FLITE_REG_CIOSAN(x) (0x200 + (4 * (x))) #define FLITE_REG_CIOSAN(x) (0x200 + (4 * (x)))
......
drivers/media/platform/omap3isp/ispreg.h
View file @ cce8ccca
This diff is collapsed.
drivers/media/platform/s3c-camif/camif-regs.h
View file @ cce8ccca
...@@ -9,6 +9,8 @@ ...@@ -9,6 +9,8 @@
#ifndef CAMIF_REGS_H_ #ifndef CAMIF_REGS_H_
#define CAMIF_REGS_H_ #define CAMIF_REGS_H_
#include <linux/bitops.h>
#include "camif-core.h" #include "camif-core.h"
#include <media/drv-intf/s3c_camif.h> #include <media/drv-intf/s3c_camif.h>
...@@ -19,7 +21,7 @@ ...@@ -19,7 +21,7 @@
/* Camera input format */ /* Camera input format */
#define S3C_CAMIF_REG_CISRCFMT 0x00 #define S3C_CAMIF_REG_CISRCFMT 0x00
#define CISRCFMT_ITU601_8BIT (1 << 31) #define CISRCFMT_ITU601_8BIT BIT(31)
#define CISRCFMT_ITU656_8BIT (0 << 31) #define CISRCFMT_ITU656_8BIT (0 << 31)
#define CISRCFMT_ORDER422_YCBYCR (0 << 14) #define CISRCFMT_ORDER422_YCBYCR (0 << 14)
#define CISRCFMT_ORDER422_YCRYCB (1 << 14) #define CISRCFMT_ORDER422_YCRYCB (1 << 14)
...@@ -30,14 +32,14 @@ ...@@ -30,14 +32,14 @@
/* Window offset */ /* Window offset */
#define S3C_CAMIF_REG_CIWDOFST 0x04 #define S3C_CAMIF_REG_CIWDOFST 0x04
#define CIWDOFST_WINOFSEN (1 << 31) #define CIWDOFST_WINOFSEN BIT(31)
#define CIWDOFST_CLROVCOFIY (1 << 30) #define CIWDOFST_CLROVCOFIY BIT(30)
#define CIWDOFST_CLROVRLB_PR (1 << 28) #define CIWDOFST_CLROVRLB_PR BIT(28)
/* #define CIWDOFST_CLROVPRFIY (1 << 27) */ /* #define CIWDOFST_CLROVPRFIY BIT(27) */
#define CIWDOFST_CLROVCOFICB (1 << 15) #define CIWDOFST_CLROVCOFICB BIT(15)
#define CIWDOFST_CLROVCOFICR (1 << 14) #define CIWDOFST_CLROVCOFICR BIT(14)
#define CIWDOFST_CLROVPRFICB (1 << 13) #define CIWDOFST_CLROVPRFICB BIT(13)
#define CIWDOFST_CLROVPRFICR (1 << 12) #define CIWDOFST_CLROVPRFICR BIT(12)
#define CIWDOFST_OFST_MASK (0x7ff << 16 | 0x7ff) #define CIWDOFST_OFST_MASK (0x7ff << 16 | 0x7ff)
/* Window offset 2 */ /* Window offset 2 */
...@@ -46,24 +48,24 @@ ...@@ -46,24 +48,24 @@
/* Global control */ /* Global control */
#define S3C_CAMIF_REG_CIGCTRL 0x08 #define S3C_CAMIF_REG_CIGCTRL 0x08
#define CIGCTRL_SWRST (1 << 31) #define CIGCTRL_SWRST BIT(31)
#define CIGCTRL_CAMRST (1 << 30) #define CIGCTRL_CAMRST BIT(30)
#define CIGCTRL_TESTPATTERN_NORMAL (0 << 27) #define CIGCTRL_TESTPATTERN_NORMAL (0 << 27)
#define CIGCTRL_TESTPATTERN_COLOR_BAR (1 << 27) #define CIGCTRL_TESTPATTERN_COLOR_BAR (1 << 27)
#define CIGCTRL_TESTPATTERN_HOR_INC (2 << 27) #define CIGCTRL_TESTPATTERN_HOR_INC (2 << 27)
#define CIGCTRL_TESTPATTERN_VER_INC (3 << 27) #define CIGCTRL_TESTPATTERN_VER_INC (3 << 27)
#define CIGCTRL_TESTPATTERN_MASK (3 << 27) #define CIGCTRL_TESTPATTERN_MASK (3 << 27)
#define CIGCTRL_INVPOLPCLK (1 << 26) #define CIGCTRL_INVPOLPCLK BIT(26)
#define CIGCTRL_INVPOLVSYNC (1 << 25) #define CIGCTRL_INVPOLVSYNC BIT(25)
#define CIGCTRL_INVPOLHREF (1 << 24) #define CIGCTRL_INVPOLHREF BIT(24)
#define CIGCTRL_IRQ_OVFEN (1 << 22) #define CIGCTRL_IRQ_OVFEN BIT(22)
#define CIGCTRL_HREF_MASK (1 << 21) #define CIGCTRL_HREF_MASK BIT(21)
#define CIGCTRL_IRQ_LEVEL (1 << 20) #define CIGCTRL_IRQ_LEVEL BIT(20)
/* IRQ_CLR_C, IRQ_CLR_P */ /* IRQ_CLR_C, IRQ_CLR_P */
#define CIGCTRL_IRQ_CLR(id) (1 << (19 - (id))) #define CIGCTRL_IRQ_CLR(id) BIT(19 - (id))
#define CIGCTRL_FIELDMODE (1 << 2) #define CIGCTRL_FIELDMODE BIT(2)
#define CIGCTRL_INVPOLFIELD (1 << 1) #define CIGCTRL_INVPOLFIELD BIT(1)
#define CIGCTRL_CAM_INTERLACE (1 << 0) #define CIGCTRL_CAM_INTERLACE BIT(0)
/* Y DMA output frame start address. n = 0..3. */ /* Y DMA output frame start address. n = 0..3. */
#define S3C_CAMIF_REG_CIYSA(id, n) (0x18 + (id) * 0x54 + (n) * 4) #define S3C_CAMIF_REG_CIYSA(id, n) (0x18 + (id) * 0x54 + (n) * 4)
...@@ -74,8 +76,8 @@ ...@@ -74,8 +76,8 @@
/* CICOTRGFMT, CIPRTRGFMT - Target format */ /* CICOTRGFMT, CIPRTRGFMT - Target format */
#define S3C_CAMIF_REG_CITRGFMT(id, _offs) (0x48 + (id) * (0x34 + (_offs))) #define S3C_CAMIF_REG_CITRGFMT(id, _offs) (0x48 + (id) * (0x34 + (_offs)))
#define CITRGFMT_IN422 (1 << 31) /* only for s3c24xx */ #define CITRGFMT_IN422 BIT(31) /* only for s3c24xx */
#define CITRGFMT_OUT422 (1 << 30) /* only for s3c24xx */ #define CITRGFMT_OUT422 BIT(30) /* only for s3c24xx */
#define CITRGFMT_OUTFORMAT_YCBCR420 (0 << 29) /* only for s3c6410 */ #define CITRGFMT_OUTFORMAT_YCBCR420 (0 << 29) /* only for s3c6410 */
#define CITRGFMT_OUTFORMAT_YCBCR422 (1 << 29) /* only for s3c6410 */ #define CITRGFMT_OUTFORMAT_YCBCR422 (1 << 29) /* only for s3c6410 */
#define CITRGFMT_OUTFORMAT_YCBCR422I (2 << 29) /* only for s3c6410 */ #define CITRGFMT_OUTFORMAT_YCBCR422I (2 << 29) /* only for s3c6410 */
...@@ -88,7 +90,7 @@ ...@@ -88,7 +90,7 @@
#define CITRGFMT_FLIP_180 (3 << 14) #define CITRGFMT_FLIP_180 (3 << 14)
#define CITRGFMT_FLIP_MASK (3 << 14) #define CITRGFMT_FLIP_MASK (3 << 14)
/* Preview path only */ /* Preview path only */
#define CITRGFMT_ROT90_PR (1 << 13) #define CITRGFMT_ROT90_PR BIT(13)
#define CITRGFMT_TARGETVSIZE(x) ((x) << 0) #define CITRGFMT_TARGETVSIZE(x) ((x) << 0)
#define CITRGFMT_TARGETSIZE_MASK ((0x1fff << 16) | 0x1fff) #define CITRGFMT_TARGETSIZE_MASK ((0x1fff << 16) | 0x1fff)
...@@ -102,7 +104,7 @@ ...@@ -102,7 +104,7 @@
#define CICTRL_RGBBURST2(x) ((x) << 14) #define CICTRL_RGBBURST2(x) ((x) << 14)
#define CICTRL_CBURST1(x) ((x) << 9) #define CICTRL_CBURST1(x) ((x) << 9)
#define CICTRL_CBURST2(x) ((x) << 4) #define CICTRL_CBURST2(x) ((x) << 4)
#define CICTRL_LASTIRQ_ENABLE (1 << 2) #define CICTRL_LASTIRQ_ENABLE BIT(2)
#define CICTRL_ORDER422_MASK (3 << 0) #define CICTRL_ORDER422_MASK (3 << 0)
/* CICOSCPRERATIO, CIPRSCPRERATIO. Pre-scaler control 1. */ /* CICOSCPRERATIO, CIPRSCPRERATIO. Pre-scaler control 1. */
...@@ -113,22 +115,22 @@ ...@@ -113,22 +115,22 @@
/* CICOSCCTRL, CIPRSCCTRL. Main scaler control. */ /* CICOSCCTRL, CIPRSCCTRL. Main scaler control. */
#define S3C_CAMIF_REG_CISCCTRL(id, _offs) (0x58 + (id) * (0x34 + (_offs))) #define S3C_CAMIF_REG_CISCCTRL(id, _offs) (0x58 + (id) * (0x34 + (_offs)))
#define CISCCTRL_SCALERBYPASS (1 << 31) #define CISCCTRL_SCALERBYPASS BIT(31)
/* s3c244x preview path only, s3c64xx both */ /* s3c244x preview path only, s3c64xx both */
#define CIPRSCCTRL_SAMPLE (1 << 31) #define CIPRSCCTRL_SAMPLE BIT(31)
/* 0 - 16-bit RGB, 1 - 24-bit RGB */ /* 0 - 16-bit RGB, 1 - 24-bit RGB */
#define CIPRSCCTRL_RGB_FORMAT_24BIT (1 << 30) /* only for s3c244x */ #define CIPRSCCTRL_RGB_FORMAT_24BIT BIT(30) /* only for s3c244x */
#define CIPRSCCTRL_SCALEUP_H (1 << 29) /* only for s3c244x */ #define CIPRSCCTRL_SCALEUP_H BIT(29) /* only for s3c244x */
#define CIPRSCCTRL_SCALEUP_V (1 << 28) /* only for s3c244x */ #define CIPRSCCTRL_SCALEUP_V BIT(28) /* only for s3c244x */
/* s3c64xx */ /* s3c64xx */
#define CISCCTRL_SCALEUP_H (1 << 30) #define CISCCTRL_SCALEUP_H BIT(30)
#define CISCCTRL_SCALEUP_V (1 << 29) #define CISCCTRL_SCALEUP_V BIT(29)
#define CISCCTRL_SCALEUP_MASK (0x3 << 29) #define CISCCTRL_SCALEUP_MASK (0x3 << 29)
#define CISCCTRL_CSCR2Y_WIDE (1 << 28) #define CISCCTRL_CSCR2Y_WIDE BIT(28)
#define CISCCTRL_CSCY2R_WIDE (1 << 27) #define CISCCTRL_CSCY2R_WIDE BIT(27)
#define CISCCTRL_LCDPATHEN_FIFO (1 << 26) #define CISCCTRL_LCDPATHEN_FIFO BIT(26)
#define CISCCTRL_INTERLACE (1 << 25) #define CISCCTRL_INTERLACE BIT(25)
#define CISCCTRL_SCALERSTART (1 << 15) #define CISCCTRL_SCALERSTART BIT(15)
#define CISCCTRL_INRGB_FMT_RGB565 (0 << 13) #define CISCCTRL_INRGB_FMT_RGB565 (0 << 13)
#define CISCCTRL_INRGB_FMT_RGB666 (1 << 13) #define CISCCTRL_INRGB_FMT_RGB666 (1 << 13)
#define CISCCTRL_INRGB_FMT_RGB888 (2 << 13) #define CISCCTRL_INRGB_FMT_RGB888 (2 << 13)
...@@ -137,8 +139,8 @@ ...@@ -137,8 +139,8 @@
#define CISCCTRL_OUTRGB_FMT_RGB666 (1 << 11) #define CISCCTRL_OUTRGB_FMT_RGB666 (1 << 11)
#define CISCCTRL_OUTRGB_FMT_RGB888 (2 << 11) #define CISCCTRL_OUTRGB_FMT_RGB888 (2 << 11)
#define CISCCTRL_OUTRGB_FMT_MASK (3 << 11) #define CISCCTRL_OUTRGB_FMT_MASK (3 << 11)
#define CISCCTRL_EXTRGB_EXTENSION (1 << 10) #define CISCCTRL_EXTRGB_EXTENSION BIT(10)
#define CISCCTRL_ONE2ONE (1 << 9) #define CISCCTRL_ONE2ONE BIT(9)
#define CISCCTRL_MAIN_RATIO_MASK (0x1ff << 16 | 0x1ff) #define CISCCTRL_MAIN_RATIO_MASK (0x1ff << 16 | 0x1ff)
/* CICOTAREA, CIPRTAREA. Target area for DMA (Hsize x Vsize). */ /* CICOTAREA, CIPRTAREA. Target area for DMA (Hsize x Vsize). */
...@@ -147,38 +149,38 @@ ...@@ -147,38 +149,38 @@
/* Codec (id = 0) or preview (id = 1) path status. */ /* Codec (id = 0) or preview (id = 1) path status. */
#define S3C_CAMIF_REG_CISTATUS(id, _offs) (0x64 + (id) * (0x34 + (_offs))) #define S3C_CAMIF_REG_CISTATUS(id, _offs) (0x64 + (id) * (0x34 + (_offs)))
#define CISTATUS_OVFIY_STATUS (1 << 31) #define CISTATUS_OVFIY_STATUS BIT(31)
#define CISTATUS_OVFICB_STATUS (1 << 30) #define CISTATUS_OVFICB_STATUS BIT(30)
#define CISTATUS_OVFICR_STATUS (1 << 29) #define CISTATUS_OVFICR_STATUS BIT(29)
#define CISTATUS_OVF_MASK (0x7 << 29) #define CISTATUS_OVF_MASK (0x7 << 29)
#define CIPRSTATUS_OVF_MASK (0x3 << 30) #define CIPRSTATUS_OVF_MASK (0x3 << 30)
#define CISTATUS_VSYNC_STATUS (1 << 28) #define CISTATUS_VSYNC_STATUS BIT(28)
#define CISTATUS_FRAMECNT_MASK (3 << 26) #define CISTATUS_FRAMECNT_MASK (3 << 26)
#define CISTATUS_FRAMECNT(__reg) (((__reg) >> 26) & 0x3) #define CISTATUS_FRAMECNT(__reg) (((__reg) >> 26) & 0x3)
#define CISTATUS_WINOFSTEN_STATUS (1 << 25) #define CISTATUS_WINOFSTEN_STATUS BIT(25)
#define CISTATUS_IMGCPTEN_STATUS (1 << 22) #define CISTATUS_IMGCPTEN_STATUS BIT(22)
#define CISTATUS_IMGCPTENSC_STATUS (1 << 21) #define CISTATUS_IMGCPTENSC_STATUS BIT(21)
#define CISTATUS_VSYNC_A_STATUS (1 << 20) #define CISTATUS_VSYNC_A_STATUS BIT(20)
#define CISTATUS_FRAMEEND_STATUS (1 << 19) /* 17 on s3c64xx */ #define CISTATUS_FRAMEEND_STATUS BIT(19) /* 17 on s3c64xx */
/* Image capture enable */ /* Image capture enable */
#define S3C_CAMIF_REG_CIIMGCPT(_offs) (0xa0 + (_offs)) #define S3C_CAMIF_REG_CIIMGCPT(_offs) (0xa0 + (_offs))
#define CIIMGCPT_IMGCPTEN (1 << 31) #define CIIMGCPT_IMGCPTEN BIT(31)
#define CIIMGCPT_IMGCPTEN_SC(id) (1 << (30 - (id))) #define CIIMGCPT_IMGCPTEN_SC(id) BIT(30 - (id))
/* Frame control: 1 - one-shot, 0 - free run */ /* Frame control: 1 - one-shot, 0 - free run */
#define CIIMGCPT_CPT_FREN_ENABLE(id) (1 << (25 - (id))) #define CIIMGCPT_CPT_FREN_ENABLE(id) BIT(25 - (id))
#define CIIMGCPT_CPT_FRMOD_ENABLE (0 << 18) #define CIIMGCPT_CPT_FRMOD_ENABLE (0 << 18)
#define CIIMGCPT_CPT_FRMOD_CNT (1 << 18) #define CIIMGCPT_CPT_FRMOD_CNT BIT(18)
/* Capture sequence */ /* Capture sequence */
#define S3C_CAMIF_REG_CICPTSEQ 0xc4 #define S3C_CAMIF_REG_CICPTSEQ 0xc4
/* Image effects */ /* Image effects */
#define S3C_CAMIF_REG_CIIMGEFF(_offs) (0xb0 + (_offs)) #define S3C_CAMIF_REG_CIIMGEFF(_offs) (0xb0 + (_offs))
#define CIIMGEFF_IE_ENABLE(id) (1 << (30 + (id))) #define CIIMGEFF_IE_ENABLE(id) BIT(30 + (id))
#define CIIMGEFF_IE_ENABLE_MASK (3 << 30) #define CIIMGEFF_IE_ENABLE_MASK (3 << 30)
/* Image effect: 1 - after scaler, 0 - before scaler */ /* Image effect: 1 - after scaler, 0 - before scaler */
#define CIIMGEFF_IE_AFTER_SC (1 << 29) #define CIIMGEFF_IE_AFTER_SC BIT(29)
#define CIIMGEFF_FIN_MASK (7 << 26) #define CIIMGEFF_FIN_MASK (7 << 26)
#define CIIMGEFF_FIN_BYPASS (0 << 26) #define CIIMGEFF_FIN_BYPASS (0 << 26)
#define CIIMGEFF_FIN_ARBITRARY (1 << 26) #define CIIMGEFF_FIN_ARBITRARY (1 << 26)
...@@ -207,8 +209,8 @@ ...@@ -207,8 +209,8 @@
/* Real input DMA data size. n = 0 - codec, 1 - preview. */ /* Real input DMA data size. n = 0 - codec, 1 - preview. */
#define S3C_CAMIF_REG_MSWIDTH(id) (0xf8 + (id) * 0x2c) #define S3C_CAMIF_REG_MSWIDTH(id) (0xf8 + (id) * 0x2c)
#define AUTOLOAD_ENABLE (1 << 31) #define AUTOLOAD_ENABLE BIT(31)
#define ADDR_CH_DIS (1 << 30) #define ADDR_CH_DIS BIT(30)
#define MSHEIGHT(x) (((x) & 0x3ff) << 16) #define MSHEIGHT(x) (((x) & 0x3ff) << 16)
#define MSWIDTH(x) ((x) & 0x3ff) #define MSWIDTH(x) ((x) & 0x3ff)
...@@ -219,12 +221,12 @@ ...@@ -219,12 +221,12 @@
#define MSCTRL_ORDER422_M_CBYCRY (2 << 4) #define MSCTRL_ORDER422_M_CBYCRY (2 << 4)
#define MSCTRL_ORDER422_M_CRYCBY (3 << 4) #define MSCTRL_ORDER422_M_CRYCBY (3 << 4)
/* 0 - camera, 1 - DMA */ /* 0 - camera, 1 - DMA */
#define MSCTRL_SEL_DMA_CAM (1 << 3) #define MSCTRL_SEL_DMA_CAM BIT(3)
#define MSCTRL_INFORMAT_M_YCBCR420 (0 << 1) #define MSCTRL_INFORMAT_M_YCBCR420 (0 << 1)
#define MSCTRL_INFORMAT_M_YCBCR422 (1 << 1) #define MSCTRL_INFORMAT_M_YCBCR422 (1 << 1)
#define MSCTRL_INFORMAT_M_YCBCR422I (2 << 1) #define MSCTRL_INFORMAT_M_YCBCR422I (2 << 1)
#define MSCTRL_INFORMAT_M_RGB (3 << 1) #define MSCTRL_INFORMAT_M_RGB (3 << 1)
#define MSCTRL_ENVID_M (1 << 0) #define MSCTRL_ENVID_M BIT(0)
/* CICOSCOSY, CIPRSCOSY. Scan line Y/Cb/Cr offset. */ /* CICOSCOSY, CIPRSCOSY. Scan line Y/Cb/Cr offset. */
#define S3C_CAMIF_REG_CISSY(id) (0x12c + (id) * 0x0c) #define S3C_CAMIF_REG_CISSY(id) (0x12c + (id) * 0x0c)
......
drivers/media/platform/tegra-cec/tegra_cec.h
View file @ cce8ccca
...@@ -34,24 +34,24 @@ ...@@ -34,24 +34,24 @@
#define TEGRA_CEC_HWCTRL_RX_LADDR_MASK 0x7fff #define TEGRA_CEC_HWCTRL_RX_LADDR_MASK 0x7fff
#define TEGRA_CEC_HWCTRL_RX_LADDR(x) \ #define TEGRA_CEC_HWCTRL_RX_LADDR(x) \
((x) & TEGRA_CEC_HWCTRL_RX_LADDR_MASK) ((x) & TEGRA_CEC_HWCTRL_RX_LADDR_MASK)
#define TEGRA_CEC_HWCTRL_RX_SNOOP (1 << 15) #define TEGRA_CEC_HWCTRL_RX_SNOOP BIT(15)
#define TEGRA_CEC_HWCTRL_RX_NAK_MODE (1 << 16) #define TEGRA_CEC_HWCTRL_RX_NAK_MODE BIT(16)
#define TEGRA_CEC_HWCTRL_TX_NAK_MODE (1 << 24) #define TEGRA_CEC_HWCTRL_TX_NAK_MODE BIT(24)
#define TEGRA_CEC_HWCTRL_FAST_SIM_MODE (1 << 30) #define TEGRA_CEC_HWCTRL_FAST_SIM_MODE BIT(30)
#define TEGRA_CEC_HWCTRL_TX_RX_MODE (1 << 31) #define TEGRA_CEC_HWCTRL_TX_RX_MODE BIT(31)
#define TEGRA_CEC_INPUT_FILTER_MODE (1 << 31) #define TEGRA_CEC_INPUT_FILTER_MODE BIT(31)
#define TEGRA_CEC_INPUT_FILTER_FIFO_LENGTH_SHIFT 0 #define TEGRA_CEC_INPUT_FILTER_FIFO_LENGTH_SHIFT 0
#define TEGRA_CEC_TX_REG_DATA_SHIFT 0 #define TEGRA_CEC_TX_REG_DATA_SHIFT 0
#define TEGRA_CEC_TX_REG_EOM (1 << 8) #define TEGRA_CEC_TX_REG_EOM BIT(8)
#define TEGRA_CEC_TX_REG_BCAST (1 << 12) #define TEGRA_CEC_TX_REG_BCAST BIT(12)
#define TEGRA_CEC_TX_REG_START_BIT (1 << 16) #define TEGRA_CEC_TX_REG_START_BIT BIT(16)
#define TEGRA_CEC_TX_REG_RETRY (1 << 17) #define TEGRA_CEC_TX_REG_RETRY BIT(17)
#define TEGRA_CEC_RX_REGISTER_SHIFT 0 #define TEGRA_CEC_RX_REGISTER_SHIFT 0
#define TEGRA_CEC_RX_REGISTER_EOM (1 << 8) #define TEGRA_CEC_RX_REGISTER_EOM BIT(8)
#define TEGRA_CEC_RX_REGISTER_ACK (1 << 9) #define TEGRA_CEC_RX_REGISTER_ACK BIT(9)
#define TEGRA_CEC_RX_TIM0_START_BIT_MAX_LO_TIME_SHIFT 0 #define TEGRA_CEC_RX_TIM0_START_BIT_MAX_LO_TIME_SHIFT 0
#define TEGRA_CEC_RX_TIM0_START_BIT_MIN_LO_TIME_SHIFT 8 #define TEGRA_CEC_RX_TIM0_START_BIT_MIN_LO_TIME_SHIFT 8
...@@ -79,38 +79,38 @@ ...@@ -79,38 +79,38 @@
#define TEGRA_CEC_TX_TIM2_BUS_IDLE_TIME_NEW_FRAME_SHIFT 4 #define TEGRA_CEC_TX_TIM2_BUS_IDLE_TIME_NEW_FRAME_SHIFT 4
#define TEGRA_CEC_TX_TIM2_BUS_IDLE_TIME_RETRY_FRAME_SHIFT 8 #define TEGRA_CEC_TX_TIM2_BUS_IDLE_TIME_RETRY_FRAME_SHIFT 8
#define TEGRA_CEC_INT_STAT_TX_REGISTER_EMPTY (1 << 0) #define TEGRA_CEC_INT_STAT_TX_REGISTER_EMPTY BIT(0)
#define TEGRA_CEC_INT_STAT_TX_REGISTER_UNDERRUN (1 << 1) #define TEGRA_CEC_INT_STAT_TX_REGISTER_UNDERRUN BIT(1)
#define TEGRA_CEC_INT_STAT_TX_FRAME_OR_BLOCK_NAKD (1 << 2) #define TEGRA_CEC_INT_STAT_TX_FRAME_OR_BLOCK_NAKD BIT(2)
#define TEGRA_CEC_INT_STAT_TX_ARBITRATION_FAILED (1 << 3) #define TEGRA_CEC_INT_STAT_TX_ARBITRATION_FAILED BIT(3)
#define TEGRA_CEC_INT_STAT_TX_BUS_ANOMALY_DETECTED (1 << 4) #define TEGRA_CEC_INT_STAT_TX_BUS_ANOMALY_DETECTED BIT(4)
#define TEGRA_CEC_INT_STAT_TX_FRAME_TRANSMITTED (1 << 5) #define TEGRA_CEC_INT_STAT_TX_FRAME_TRANSMITTED BIT(5)
#define TEGRA_CEC_INT_STAT_RX_REGISTER_FULL (1 << 8) #define TEGRA_CEC_INT_STAT_RX_REGISTER_FULL BIT(8)
#define TEGRA_CEC_INT_STAT_RX_REGISTER_OVERRUN (1 << 9) #define TEGRA_CEC_INT_STAT_RX_REGISTER_OVERRUN BIT(9)
#define TEGRA_CEC_INT_STAT_RX_START_BIT_DETECTED (1 << 10) #define TEGRA_CEC_INT_STAT_RX_START_BIT_DETECTED BIT(10)
#define TEGRA_CEC_INT_STAT_RX_BUS_ANOMALY_DETECTED (1 << 11) #define TEGRA_CEC_INT_STAT_RX_BUS_ANOMALY_DETECTED BIT(11)
#define TEGRA_CEC_INT_STAT_RX_BUS_ERROR_DETECTED (1 << 12) #define TEGRA_CEC_INT_STAT_RX_BUS_ERROR_DETECTED BIT(12)
#define TEGRA_CEC_INT_STAT_FILTERED_RX_DATA_PIN_TRANSITION_H2L (1 << 13) #define TEGRA_CEC_INT_STAT_FILTERED_RX_DATA_PIN_TRANSITION_H2L BIT(13)
#define TEGRA_CEC_INT_STAT_FILTERED_RX_DATA_PIN_TRANSITION_L2H (1 << 14) #define TEGRA_CEC_INT_STAT_FILTERED_RX_DATA_PIN_TRANSITION_L2H BIT(14)
#define TEGRA_CEC_INT_MASK_TX_REGISTER_EMPTY (1 << 0) #define TEGRA_CEC_INT_MASK_TX_REGISTER_EMPTY BIT(0)
#define TEGRA_CEC_INT_MASK_TX_REGISTER_UNDERRUN (1 << 1) #define TEGRA_CEC_INT_MASK_TX_REGISTER_UNDERRUN BIT(1)
#define TEGRA_CEC_INT_MASK_TX_FRAME_OR_BLOCK_NAKD (1 << 2) #define TEGRA_CEC_INT_MASK_TX_FRAME_OR_BLOCK_NAKD BIT(2)
#define TEGRA_CEC_INT_MASK_TX_ARBITRATION_FAILED (1 << 3) #define TEGRA_CEC_INT_MASK_TX_ARBITRATION_FAILED BIT(3)
#define TEGRA_CEC_INT_MASK_TX_BUS_ANOMALY_DETECTED (1 << 4) #define TEGRA_CEC_INT_MASK_TX_BUS_ANOMALY_DETECTED BIT(4)
#define TEGRA_CEC_INT_MASK_TX_FRAME_TRANSMITTED (1 << 5) #define TEGRA_CEC_INT_MASK_TX_FRAME_TRANSMITTED BIT(5)
#define TEGRA_CEC_INT_MASK_RX_REGISTER_FULL (1 << 8) #define TEGRA_CEC_INT_MASK_RX_REGISTER_FULL BIT(8)
#define TEGRA_CEC_INT_MASK_RX_REGISTER_OVERRUN (1 << 9) #define TEGRA_CEC_INT_MASK_RX_REGISTER_OVERRUN BIT(9)
#define TEGRA_CEC_INT_MASK_RX_START_BIT_DETECTED (1 << 10) #define TEGRA_CEC_INT_MASK_RX_START_BIT_DETECTED BIT(10)
#define TEGRA_CEC_INT_MASK_RX_BUS_ANOMALY_DETECTED (1 << 11) #define TEGRA_CEC_INT_MASK_RX_BUS_ANOMALY_DETECTED BIT(11)
#define TEGRA_CEC_INT_MASK_RX_BUS_ERROR_DETECTED (1 << 12) #define TEGRA_CEC_INT_MASK_RX_BUS_ERROR_DETECTED BIT(12)
#define TEGRA_CEC_INT_MASK_FILTERED_RX_DATA_PIN_TRANSITION_H2L (1 << 13) #define TEGRA_CEC_INT_MASK_FILTERED_RX_DATA_PIN_TRANSITION_H2L BIT(13)
#define TEGRA_CEC_INT_MASK_FILTERED_RX_DATA_PIN_TRANSITION_L2H (1 << 14) #define TEGRA_CEC_INT_MASK_FILTERED_RX_DATA_PIN_TRANSITION_L2H BIT(14)
#define TEGRA_CEC_HW_DEBUG_TX_DURATION_COUNT_SHIFT 0 #define TEGRA_CEC_HW_DEBUG_TX_DURATION_COUNT_SHIFT 0
#define TEGRA_CEC_HW_DEBUG_TX_TXBIT_COUNT_SHIFT 17 #define TEGRA_CEC_HW_DEBUG_TX_TXBIT_COUNT_SHIFT 17
#define TEGRA_CEC_HW_DEBUG_TX_STATE_SHIFT 21 #define TEGRA_CEC_HW_DEBUG_TX_STATE_SHIFT 21
#define TEGRA_CEC_HW_DEBUG_TX_FORCELOOUT (1 << 25) #define TEGRA_CEC_HW_DEBUG_TX_FORCELOOUT BIT(25)
#define TEGRA_CEC_HW_DEBUG_TX_TXDATABIT_SAMPLE_TIMER (1 << 26) #define TEGRA_CEC_HW_DEBUG_TX_TXDATABIT_SAMPLE_TIMER BIT(26)
#endif /* TEGRA_CEC_H */ #endif /* TEGRA_CEC_H */
drivers/media/platform/ti-vpe/vpe_regs.h
View file @ cce8ccca
...@@ -48,24 +48,24 @@ ...@@ -48,24 +48,24 @@
#define VPE_INT0_ENABLE0_SET 0x0030 #define VPE_INT0_ENABLE0_SET 0x0030
#define VPE_INT0_ENABLE0 VPE_INT0_ENABLE0_SET #define VPE_INT0_ENABLE0 VPE_INT0_ENABLE0_SET
#define VPE_INT0_ENABLE0_CLR 0x0038 #define VPE_INT0_ENABLE0_CLR 0x0038
#define VPE_INT0_LIST0_COMPLETE (1 << 0) #define VPE_INT0_LIST0_COMPLETE BIT(0)
#define VPE_INT0_LIST0_NOTIFY (1 << 1) #define VPE_INT0_LIST0_NOTIFY BIT(1)
#define VPE_INT0_LIST1_COMPLETE (1 << 2) #define VPE_INT0_LIST1_COMPLETE BIT(2)
#define VPE_INT0_LIST1_NOTIFY (1 << 3) #define VPE_INT0_LIST1_NOTIFY BIT(3)
#define VPE_INT0_LIST2_COMPLETE (1 << 4) #define VPE_INT0_LIST2_COMPLETE BIT(4)
#define VPE_INT0_LIST2_NOTIFY (1 << 5) #define VPE_INT0_LIST2_NOTIFY BIT(5)
#define VPE_INT0_LIST3_COMPLETE (1 << 6) #define VPE_INT0_LIST3_COMPLETE BIT(6)
#define VPE_INT0_LIST3_NOTIFY (1 << 7) #define VPE_INT0_LIST3_NOTIFY BIT(7)
#define VPE_INT0_LIST4_COMPLETE (1 << 8) #define VPE_INT0_LIST4_COMPLETE BIT(8)
#define VPE_INT0_LIST4_NOTIFY (1 << 9) #define VPE_INT0_LIST4_NOTIFY BIT(9)
#define VPE_INT0_LIST5_COMPLETE (1 << 10) #define VPE_INT0_LIST5_COMPLETE BIT(10)
#define VPE_INT0_LIST5_NOTIFY (1 << 11) #define VPE_INT0_LIST5_NOTIFY BIT(11)
#define VPE_INT0_LIST6_COMPLETE (1 << 12) #define VPE_INT0_LIST6_COMPLETE BIT(12)
#define VPE_INT0_LIST6_NOTIFY (1 << 13) #define VPE_INT0_LIST6_NOTIFY BIT(13)
#define VPE_INT0_LIST7_COMPLETE (1 << 14) #define VPE_INT0_LIST7_COMPLETE BIT(14)
#define VPE_INT0_LIST7_NOTIFY (1 << 15) #define VPE_INT0_LIST7_NOTIFY BIT(15)
#define VPE_INT0_DESCRIPTOR (1 << 16) #define VPE_INT0_DESCRIPTOR BIT(16)
#define VPE_DEI_FMD_INT (1 << 18) #define VPE_DEI_FMD_INT BIT(18)
#define VPE_INT0_STATUS1_RAW_SET 0x0024 #define VPE_INT0_STATUS1_RAW_SET 0x0024
#define VPE_INT0_STATUS1_RAW VPE_INT0_STATUS1_RAW_SET #define VPE_INT0_STATUS1_RAW VPE_INT0_STATUS1_RAW_SET
...@@ -74,21 +74,21 @@ ...@@ -74,21 +74,21 @@
#define VPE_INT0_ENABLE1_SET 0x0034 #define VPE_INT0_ENABLE1_SET 0x0034
#define VPE_INT0_ENABLE1 VPE_INT0_ENABLE1_SET #define VPE_INT0_ENABLE1 VPE_INT0_ENABLE1_SET
#define VPE_INT0_ENABLE1_CLR 0x003c #define VPE_INT0_ENABLE1_CLR 0x003c
#define VPE_INT0_CHANNEL_GROUP0 (1 << 0) #define VPE_INT0_CHANNEL_GROUP0 BIT(0)
#define VPE_INT0_CHANNEL_GROUP1 (1 << 1) #define VPE_INT0_CHANNEL_GROUP1 BIT(1)
#define VPE_INT0_CHANNEL_GROUP2 (1 << 2) #define VPE_INT0_CHANNEL_GROUP2 BIT(2)
#define VPE_INT0_CHANNEL_GROUP3 (1 << 3) #define VPE_INT0_CHANNEL_GROUP3 BIT(3)
#define VPE_INT0_CHANNEL_GROUP4 (1 << 4) #define VPE_INT0_CHANNEL_GROUP4 BIT(4)
#define VPE_INT0_CHANNEL_GROUP5 (1 << 5) #define VPE_INT0_CHANNEL_GROUP5 BIT(5)
#define VPE_INT0_CLIENT (1 << 7) #define VPE_INT0_CLIENT BIT(7)
#define VPE_DEI_ERROR_INT (1 << 16) #define VPE_DEI_ERROR_INT BIT(16)
#define VPE_DS1_UV_ERROR_INT (1 << 22) #define VPE_DS1_UV_ERROR_INT BIT(22)
#define VPE_INTC_EOI 0x00a0 #define VPE_INTC_EOI 0x00a0
#define VPE_CLK_ENABLE 0x0100 #define VPE_CLK_ENABLE 0x0100
#define VPE_VPEDMA_CLK_ENABLE (1 << 0) #define VPE_VPEDMA_CLK_ENABLE BIT(0)
#define VPE_DATA_PATH_CLK_ENABLE (1 << 1) #define VPE_DATA_PATH_CLK_ENABLE BIT(1)
#define VPE_CLK_RESET 0x0104 #define VPE_CLK_RESET 0x0104
#define VPE_VPDMA_CLK_RESET_MASK 0x1 #define VPE_VPDMA_CLK_RESET_MASK 0x1
...@@ -101,11 +101,11 @@ ...@@ -101,11 +101,11 @@
#define VPE_CLK_FORMAT_SELECT 0x010c #define VPE_CLK_FORMAT_SELECT 0x010c
#define VPE_CSC_SRC_SELECT_MASK 0x03 #define VPE_CSC_SRC_SELECT_MASK 0x03
#define VPE_CSC_SRC_SELECT_SHIFT 0 #define VPE_CSC_SRC_SELECT_SHIFT 0
#define VPE_RGB_OUT_SELECT (1 << 8) #define VPE_RGB_OUT_SELECT BIT(8)
#define VPE_DS_SRC_SELECT_MASK 0x07 #define VPE_DS_SRC_SELECT_MASK 0x07
#define VPE_DS_SRC_SELECT_SHIFT 9 #define VPE_DS_SRC_SELECT_SHIFT 9
#define VPE_DS_BYPASS (1 << 16) #define VPE_DS_BYPASS BIT(16)
#define VPE_COLOR_SEPARATE_422 (1 << 18) #define VPE_COLOR_SEPARATE_422 BIT(18)
#define VPE_DS_SRC_DEI_SCALER (5 << VPE_DS_SRC_SELECT_SHIFT) #define VPE_DS_SRC_DEI_SCALER (5 << VPE_DS_SRC_SELECT_SHIFT)
#define VPE_CSC_SRC_DEI_SCALER (3 << VPE_CSC_SRC_SELECT_SHIFT) #define VPE_CSC_SRC_DEI_SCALER (3 << VPE_CSC_SRC_SELECT_SHIFT)
...@@ -115,8 +115,8 @@ ...@@ -115,8 +115,8 @@
#define VPE_RANGE_RANGE_MAP_Y_SHIFT 0 #define VPE_RANGE_RANGE_MAP_Y_SHIFT 0
#define VPE_RANGE_RANGE_MAP_UV_MASK 0x07 #define VPE_RANGE_RANGE_MAP_UV_MASK 0x07
#define VPE_RANGE_RANGE_MAP_UV_SHIFT 3 #define VPE_RANGE_RANGE_MAP_UV_SHIFT 3
#define VPE_RANGE_MAP_ON (1 << 6) #define VPE_RANGE_MAP_ON BIT(6)
#define VPE_RANGE_REDUCTION_ON (1 << 28) #define VPE_RANGE_REDUCTION_ON BIT(28)
/* VPE chrominance upsampler regs */ /* VPE chrominance upsampler regs */
#define VPE_US1_R0 0x0304 #define VPE_US1_R0 0x0304
...@@ -195,13 +195,13 @@ ...@@ -195,13 +195,13 @@
#define VPE_DEI_WIDTH_SHIFT 0 #define VPE_DEI_WIDTH_SHIFT 0
#define VPE_DEI_HEIGHT_MASK 0x07ff #define VPE_DEI_HEIGHT_MASK 0x07ff
#define VPE_DEI_HEIGHT_SHIFT 16 #define VPE_DEI_HEIGHT_SHIFT 16
#define VPE_DEI_INTERLACE_BYPASS (1 << 29) #define VPE_DEI_INTERLACE_BYPASS BIT(29)
#define VPE_DEI_FIELD_FLUSH (1 << 30) #define VPE_DEI_FIELD_FLUSH BIT(30)
#define VPE_DEI_PROGRESSIVE (1 << 31) #define VPE_DEI_PROGRESSIVE BIT(31)
#define VPE_MDT_BYPASS 0x0604 #define VPE_MDT_BYPASS 0x0604
#define VPE_MDT_TEMPMAX_BYPASS (1 << 0) #define VPE_MDT_TEMPMAX_BYPASS BIT(0)
#define VPE_MDT_SPATMAX_BYPASS (1 << 1) #define VPE_MDT_SPATMAX_BYPASS BIT(1)
#define VPE_MDT_SF_THRESHOLD 0x0608 #define VPE_MDT_SF_THRESHOLD 0x0608
#define VPE_MDT_SF_SC_THR1_MASK 0xff #define VPE_MDT_SF_SC_THR1_MASK 0xff
...@@ -214,8 +214,8 @@ ...@@ -214,8 +214,8 @@
#define VPE_EDI_CONFIG 0x060c #define VPE_EDI_CONFIG 0x060c
#define VPE_EDI_INP_MODE_MASK 0x03 #define VPE_EDI_INP_MODE_MASK 0x03
#define VPE_EDI_INP_MODE_SHIFT 0 #define VPE_EDI_INP_MODE_SHIFT 0
#define VPE_EDI_ENABLE_3D (1 << 2) #define VPE_EDI_ENABLE_3D BIT(2)
#define VPE_EDI_ENABLE_CHROMA_3D (1 << 3) #define VPE_EDI_ENABLE_CHROMA_3D BIT(3)
#define VPE_EDI_CHROMA3D_COR_THR_MASK 0xff #define VPE_EDI_CHROMA3D_COR_THR_MASK 0xff
#define VPE_EDI_CHROMA3D_COR_THR_SHIFT 8 #define VPE_EDI_CHROMA3D_COR_THR_SHIFT 8
#define VPE_EDI_DIR_COR_LOWER_THR_MASK 0xff #define VPE_EDI_DIR_COR_LOWER_THR_MASK 0xff
...@@ -268,7 +268,7 @@ ...@@ -268,7 +268,7 @@
#define VPE_FMD_WINDOW_MINX_SHIFT 0 #define VPE_FMD_WINDOW_MINX_SHIFT 0
#define VPE_FMD_WINDOW_MAXX_MASK 0x07ff #define VPE_FMD_WINDOW_MAXX_MASK 0x07ff
#define VPE_FMD_WINDOW_MAXX_SHIFT 16 #define VPE_FMD_WINDOW_MAXX_SHIFT 16
#define VPE_FMD_WINDOW_ENABLE (1 << 31) #define VPE_FMD_WINDOW_ENABLE BIT(31)
#define VPE_DEI_FMD_WINDOW_R1 0x0624 #define VPE_DEI_FMD_WINDOW_R1 0x0624
#define VPE_FMD_WINDOW_MINY_MASK 0x07ff #define VPE_FMD_WINDOW_MINY_MASK 0x07ff
...@@ -277,10 +277,10 @@ ...@@ -277,10 +277,10 @@
#define VPE_FMD_WINDOW_MAXY_SHIFT 16 #define VPE_FMD_WINDOW_MAXY_SHIFT 16
#define VPE_DEI_FMD_CONTROL_R0 0x0628 #define VPE_DEI_FMD_CONTROL_R0 0x0628
#define VPE_FMD_ENABLE (1 << 0) #define VPE_FMD_ENABLE BIT(0)
#define VPE_FMD_LOCK (1 << 1) #define VPE_FMD_LOCK BIT(1)
#define VPE_FMD_JAM_DIR (1 << 2) #define VPE_FMD_JAM_DIR BIT(2)
#define VPE_FMD_BED_ENABLE (1 << 3) #define VPE_FMD_BED_ENABLE BIT(3)
#define VPE_FMD_CAF_FIELD_THR_MASK 0xff #define VPE_FMD_CAF_FIELD_THR_MASK 0xff
#define VPE_FMD_CAF_FIELD_THR_SHIFT 16 #define VPE_FMD_CAF_FIELD_THR_SHIFT 16
#define VPE_FMD_CAF_LINE_THR_MASK 0xff #define VPE_FMD_CAF_LINE_THR_MASK 0xff
...@@ -293,7 +293,7 @@ ...@@ -293,7 +293,7 @@
#define VPE_DEI_FMD_STATUS_R0 0x0630 #define VPE_DEI_FMD_STATUS_R0 0x0630
#define VPE_FMD_CAF_MASK 0x000fffff #define VPE_FMD_CAF_MASK 0x000fffff
#define VPE_FMD_CAF_SHIFT 0 #define VPE_FMD_CAF_SHIFT 0
#define VPE_FMD_RESET (1 << 24) #define VPE_FMD_RESET BIT(24)
#define VPE_DEI_FMD_STATUS_R1 0x0634 #define VPE_DEI_FMD_STATUS_R1 0x0634
#define VPE_FMD_FIELD_DIFF_MASK 0x0fffffff #define VPE_FMD_FIELD_DIFF_MASK 0x0fffffff
......
drivers/media/platform/vsp1/vsp1_regs.h
View file @ cce8ccca
This diff is collapsed.
drivers/media/platform/xilinx/xilinx-vip.h
View file @ cce8ccca
...@@ -12,6 +12,7 @@ ...@@ -12,6 +12,7 @@
#ifndef __XILINX_VIP_H__ #ifndef __XILINX_VIP_H__
#define __XILINX_VIP_H__ #define __XILINX_VIP_H__
#include <linux/bitops.h>
#include <linux/io.h> #include <linux/io.h>
#include <media/v4l2-subdev.h> #include <media/v4l2-subdev.h>
...@@ -35,23 +36,23 @@ struct clk; ...@@ -35,23 +36,23 @@ struct clk;
/* Xilinx Video IP Control Registers */ /* Xilinx Video IP Control Registers */
#define XVIP_CTRL_CONTROL 0x0000 #define XVIP_CTRL_CONTROL 0x0000
#define XVIP_CTRL_CONTROL_SW_ENABLE (1 << 0) #define XVIP_CTRL_CONTROL_SW_ENABLE BIT(0)
#define XVIP_CTRL_CONTROL_REG_UPDATE (1 << 1) #define XVIP_CTRL_CONTROL_REG_UPDATE BIT(1)
#define XVIP_CTRL_CONTROL_BYPASS (1 << 4) #define XVIP_CTRL_CONTROL_BYPASS BIT(4)
#define XVIP_CTRL_CONTROL_TEST_PATTERN (1 << 5) #define XVIP_CTRL_CONTROL_TEST_PATTERN BIT(5)
#define XVIP_CTRL_CONTROL_FRAME_SYNC_RESET (1 << 30) #define XVIP_CTRL_CONTROL_FRAME_SYNC_RESET BIT(30)
#define XVIP_CTRL_CONTROL_SW_RESET (1 << 31) #define XVIP_CTRL_CONTROL_SW_RESET BIT(31)
#define XVIP_CTRL_STATUS 0x0004 #define XVIP_CTRL_STATUS 0x0004
#define XVIP_CTRL_STATUS_PROC_STARTED (1 << 0) #define XVIP_CTRL_STATUS_PROC_STARTED BIT(0)
#define XVIP_CTRL_STATUS_EOF (1 << 1) #define XVIP_CTRL_STATUS_EOF BIT(1)
#define XVIP_CTRL_ERROR 0x0008 #define XVIP_CTRL_ERROR 0x0008
#define XVIP_CTRL_ERROR_SLAVE_EOL_EARLY (1 << 0) #define XVIP_CTRL_ERROR_SLAVE_EOL_EARLY BIT(0)
#define XVIP_CTRL_ERROR_SLAVE_EOL_LATE (1 << 1) #define XVIP_CTRL_ERROR_SLAVE_EOL_LATE BIT(1)
#define XVIP_CTRL_ERROR_SLAVE_SOF_EARLY (1 << 2) #define XVIP_CTRL_ERROR_SLAVE_SOF_EARLY BIT(2)
#define XVIP_CTRL_ERROR_SLAVE_SOF_LATE (1 << 3) #define XVIP_CTRL_ERROR_SLAVE_SOF_LATE BIT(3)
#define XVIP_CTRL_IRQ_ENABLE 0x000c #define XVIP_CTRL_IRQ_ENABLE 0x000c
#define XVIP_CTRL_IRQ_ENABLE_PROC_STARTED (1 << 0) #define XVIP_CTRL_IRQ_ENABLE_PROC_STARTED BIT(0)
#define XVIP_CTRL_IRQ_EOF (1 << 1) #define XVIP_CTRL_IRQ_EOF BIT(1)
#define XVIP_CTRL_VERSION 0x0010 #define XVIP_CTRL_VERSION 0x0010
#define XVIP_CTRL_VERSION_MAJOR_MASK (0xff << 24) #define XVIP_CTRL_VERSION_MAJOR_MASK (0xff << 24)
#define XVIP_CTRL_VERSION_MAJOR_SHIFT 24 #define XVIP_CTRL_VERSION_MAJOR_SHIFT 24
......
drivers/media/radio/wl128x/fmdrv_common.h
View file @ cce8ccca
...@@ -159,18 +159,18 @@ struct fm_event_msg_hdr { ...@@ -159,18 +159,18 @@ struct fm_event_msg_hdr {
#define FM_DISABLE 0 #define FM_DISABLE 0
/* FLAG_GET register bits */ /* FLAG_GET register bits */
#define FM_FR_EVENT (1 << 0) #define FM_FR_EVENT BIT(0)
#define FM_BL_EVENT (1 << 1) #define FM_BL_EVENT BIT(1)
#define FM_RDS_EVENT (1 << 2) #define FM_RDS_EVENT BIT(2)
#define FM_BBLK_EVENT (1 << 3) #define FM_BBLK_EVENT BIT(3)
#define FM_LSYNC_EVENT (1 << 4) #define FM_LSYNC_EVENT BIT(4)
#define FM_LEV_EVENT (1 << 5) #define FM_LEV_EVENT BIT(5)
#define FM_IFFR_EVENT (1 << 6) #define FM_IFFR_EVENT BIT(6)
#define FM_PI_EVENT (1 << 7) #define FM_PI_EVENT BIT(7)
#define FM_PD_EVENT (1 << 8) #define FM_PD_EVENT BIT(8)
#define FM_STIC_EVENT (1 << 9) #define FM_STIC_EVENT BIT(9)
#define FM_MAL_EVENT (1 << 10) #define FM_MAL_EVENT BIT(10)
#define FM_POW_ENB_EVENT (1 << 11) #define FM_POW_ENB_EVENT BIT(11)
/* /*
* Firmware files of FM. ASIC ID and ASIC version will be appened to this, * Firmware files of FM. ASIC ID and ASIC version will be appened to this,
...@@ -268,38 +268,38 @@ struct fm_event_msg_hdr { ...@@ -268,38 +268,38 @@ struct fm_event_msg_hdr {
* Represents an RDS group type & version. * Represents an RDS group type & version.
* There are 15 groups, each group has 2 versions: A and B. * There are 15 groups, each group has 2 versions: A and B.
*/ */
#define FM_RDS_GROUP_TYPE_MASK_0A ((unsigned long)1<<0) #define FM_RDS_GROUP_TYPE_MASK_0A BIT(0)
#define FM_RDS_GROUP_TYPE_MASK_0B ((unsigned long)1<<1) #define FM_RDS_GROUP_TYPE_MASK_0B BIT(1)
#define FM_RDS_GROUP_TYPE_MASK_1A ((unsigned long)1<<2) #define FM_RDS_GROUP_TYPE_MASK_1A BIT(2)
#define FM_RDS_GROUP_TYPE_MASK_1B ((unsigned long)1<<3) #define FM_RDS_GROUP_TYPE_MASK_1B BIT(3)
#define FM_RDS_GROUP_TYPE_MASK_2A ((unsigned long)1<<4) #define FM_RDS_GROUP_TYPE_MASK_2A BIT(4)
#define FM_RDS_GROUP_TYPE_MASK_2B ((unsigned long)1<<5) #define FM_RDS_GROUP_TYPE_MASK_2B BIT(5)
#define FM_RDS_GROUP_TYPE_MASK_3A ((unsigned long)1<<6) #define FM_RDS_GROUP_TYPE_MASK_3A BIT(6)
#define FM_RDS_GROUP_TYPE_MASK_3B ((unsigned long)1<<7) #define FM_RDS_GROUP_TYPE_MASK_3B BIT(7)
#define FM_RDS_GROUP_TYPE_MASK_4A ((unsigned long)1<<8) #define FM_RDS_GROUP_TYPE_MASK_4A BIT(8)
#define FM_RDS_GROUP_TYPE_MASK_4B ((unsigned long)1<<9) #define FM_RDS_GROUP_TYPE_MASK_4B BIT(9)
#define FM_RDS_GROUP_TYPE_MASK_5A ((unsigned long)1<<10) #define FM_RDS_GROUP_TYPE_MASK_5A BIT(10)
#define FM_RDS_GROUP_TYPE_MASK_5B ((unsigned long)1<<11) #define FM_RDS_GROUP_TYPE_MASK_5B BIT(11)
#define FM_RDS_GROUP_TYPE_MASK_6A ((unsigned long)1<<12) #define FM_RDS_GROUP_TYPE_MASK_6A BIT(12)
#define FM_RDS_GROUP_TYPE_MASK_6B ((unsigned long)1<<13) #define FM_RDS_GROUP_TYPE_MASK_6B BIT(13)
#define FM_RDS_GROUP_TYPE_MASK_7A ((unsigned long)1<<14) #define FM_RDS_GROUP_TYPE_MASK_7A BIT(14)
#define FM_RDS_GROUP_TYPE_MASK_7B ((unsigned long)1<<15) #define FM_RDS_GROUP_TYPE_MASK_7B BIT(15)
#define FM_RDS_GROUP_TYPE_MASK_8A ((unsigned long)1<<16) #define FM_RDS_GROUP_TYPE_MASK_8A BIT(16)
#define FM_RDS_GROUP_TYPE_MASK_8B ((unsigned long)1<<17) #define FM_RDS_GROUP_TYPE_MASK_8B BIT(17)
#define FM_RDS_GROUP_TYPE_MASK_9A ((unsigned long)1<<18) #define FM_RDS_GROUP_TYPE_MASK_9A BIT(18)
#define FM_RDS_GROUP_TYPE_MASK_9B ((unsigned long)1<<19) #define FM_RDS_GROUP_TYPE_MASK_9B BIT(19)
#define FM_RDS_GROUP_TYPE_MASK_10A ((unsigned long)1<<20) #define FM_RDS_GROUP_TYPE_MASK_10A BIT(20)
#define FM_RDS_GROUP_TYPE_MASK_10B ((unsigned long)1<<21) #define FM_RDS_GROUP_TYPE_MASK_10B BIT(21)
#define FM_RDS_GROUP_TYPE_MASK_11A ((unsigned long)1<<22) #define FM_RDS_GROUP_TYPE_MASK_11A BIT(22)
#define FM_RDS_GROUP_TYPE_MASK_11B ((unsigned long)1<<23) #define FM_RDS_GROUP_TYPE_MASK_11B BIT(23)
#define FM_RDS_GROUP_TYPE_MASK_12A ((unsigned long)1<<24) #define FM_RDS_GROUP_TYPE_MASK_12A BIT(24)
#define FM_RDS_GROUP_TYPE_MASK_12B ((unsigned long)1<<25) #define FM_RDS_GROUP_TYPE_MASK_12B BIT(25)
#define FM_RDS_GROUP_TYPE_MASK_13A ((unsigned long)1<<26) #define FM_RDS_GROUP_TYPE_MASK_13A BIT(26)
#define FM_RDS_GROUP_TYPE_MASK_13B ((unsigned long)1<<27) #define FM_RDS_GROUP_TYPE_MASK_13B BIT(27)
#define FM_RDS_GROUP_TYPE_MASK_14A ((unsigned long)1<<28) #define FM_RDS_GROUP_TYPE_MASK_14A BIT(28)
#define FM_RDS_GROUP_TYPE_MASK_14B ((unsigned long)1<<29) #define FM_RDS_GROUP_TYPE_MASK_14B BIT(29)
#define FM_RDS_GROUP_TYPE_MASK_15A ((unsigned long)1<<30) #define FM_RDS_GROUP_TYPE_MASK_15A BIT(30)
#define FM_RDS_GROUP_TYPE_MASK_15B ((unsigned long)1<<31) #define FM_RDS_GROUP_TYPE_MASK_15B BIT(31)
/* RX Alternate Frequency info */ /* RX Alternate Frequency info */
#define FM_RDS_MIN_AF 1 #define FM_RDS_MIN_AF 1
......
drivers/staging/media/ipu3/ipu3-tables.h
View file @ cce8ccca
...@@ -4,6 +4,8 @@ ...@@ -4,6 +4,8 @@
#ifndef __IPU3_TABLES_H #ifndef __IPU3_TABLES_H
#define __IPU3_TABLES_H #define __IPU3_TABLES_H
#include <linux/bitops.h>
#include "ipu3-abi.h" #include "ipu3-abi.h"
#define IMGU_BDS_GRANULARITY 32 /* Downscaling granularity */ #define IMGU_BDS_GRANULARITY 32 /* Downscaling granularity */
...@@ -12,7 +14,7 @@ ...@@ -12,7 +14,7 @@
#define IMGU_SCALER_DOWNSCALE_4TAPS_LEN 128 #define IMGU_SCALER_DOWNSCALE_4TAPS_LEN 128
#define IMGU_SCALER_DOWNSCALE_2TAPS_LEN 64 #define IMGU_SCALER_DOWNSCALE_2TAPS_LEN 64
#define IMGU_SCALER_FP ((u32)1 << 31) /* 1.0 in fixed point */ #define IMGU_SCALER_FP BIT(31) /* 1.0 in fixed point */
#define IMGU_XNR3_VMEM_LUT_LEN 16 #define IMGU_XNR3_VMEM_LUT_LEN 16
......
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