Commit ccf0d68e authored by Scott Wood's avatar Scott Wood Committed by Kumar Gala

[POWERPC] 8xx: Fix CONFIG_PIN_TLB.

1. Move CONSISTENT_START on 8xx so that it doesn't overlap the IMMR mapping.
2. The wrong register was being loaded into SPRN_MD_RPN.
Signed-off-by: default avatarScott Wood <scottwood@freescale.com>
Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
parent d948a29e
...@@ -600,6 +600,7 @@ config CONSISTENT_START_BOOL ...@@ -600,6 +600,7 @@ config CONSISTENT_START_BOOL
config CONSISTENT_START config CONSISTENT_START
hex "Base virtual address of consistent memory pool" if CONSISTENT_START_BOOL hex "Base virtual address of consistent memory pool" if CONSISTENT_START_BOOL
default "0xfd000000" if (NOT_COHERENT_CACHE && 8xx)
default "0xff100000" if NOT_COHERENT_CACHE default "0xff100000" if NOT_COHERENT_CACHE
config CONSISTENT_SIZE_BOOL config CONSISTENT_SIZE_BOOL
......
...@@ -727,13 +727,13 @@ initial_mmu: ...@@ -727,13 +727,13 @@ initial_mmu:
mtspr SPRN_MD_TWC, r9 mtspr SPRN_MD_TWC, r9
li r11, MI_BOOTINIT /* Create RPN for address 0 */ li r11, MI_BOOTINIT /* Create RPN for address 0 */
addis r11, r11, 0x0080 /* Add 8M */ addis r11, r11, 0x0080 /* Add 8M */
mtspr SPRN_MD_RPN, r8 mtspr SPRN_MD_RPN, r11
addis r8, r8, 0x0080 /* Add 8M */ addis r8, r8, 0x0080 /* Add 8M */
mtspr SPRN_MD_EPN, r8 mtspr SPRN_MD_EPN, r8
mtspr SPRN_MD_TWC, r9 mtspr SPRN_MD_TWC, r9
addis r11, r11, 0x0080 /* Add 8M */ addis r11, r11, 0x0080 /* Add 8M */
mtspr SPRN_MD_RPN, r8 mtspr SPRN_MD_RPN, r11
#endif #endif
/* Since the cache is enabled according to the information we /* Since the cache is enabled according to the information we
......
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