Commit cda77556 authored by Philipp Zabel's avatar Philipp Zabel

gpu: ipu-v3: Allow channel burst locking on i.MX6 only

The IDMAC_LOCK_EN registers on i.MX51 have a different layout, and on
i.MX53 enabling the lock feature causes bursts to get lost. Restrict
enabling the burst lock feature to i.MX6.
Reported-by: default avatarPatrick Brünn <P.Bruenn@beckhoff.com>
Fixes: 790cb4c7 ("drm/imx: lock scanout transfers for consecutive bursts")
Tested-by: default avatarPatrick Brünn <P.Bruenn@beckhoff.com>
Signed-off-by: default avatarPhilipp Zabel <p.zabel@pengutronix.de>
parent 8a5776a5
...@@ -405,6 +405,14 @@ int ipu_idmac_lock_enable(struct ipuv3_channel *channel, int num_bursts) ...@@ -405,6 +405,14 @@ int ipu_idmac_lock_enable(struct ipuv3_channel *channel, int num_bursts)
return -EINVAL; return -EINVAL;
} }
/*
* IPUv3EX / i.MX51 has a different register layout, and on IPUv3M /
* i.MX53 channel arbitration locking doesn't seem to work properly.
* Allow enabling the lock feature on IPUv3H / i.MX6 only.
*/
if (bursts && ipu->ipu_type != IPUV3H)
return -EINVAL;
for (i = 0; i < ARRAY_SIZE(idmac_lock_en_info); i++) { for (i = 0; i < ARRAY_SIZE(idmac_lock_en_info); i++) {
if (channel->num == idmac_lock_en_info[i].chnum) if (channel->num == idmac_lock_en_info[i].chnum)
break; break;
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment