Commit cec24b8b authored by Linus Torvalds's avatar Linus Torvalds

Merge tag 'char-misc-6.4-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc

Pull char/misc drivers updates from Greg KH:
 "Here is the "big" set of char/misc and other driver subsystems for
  6.4-rc1.

  It's pretty big, but due to the removal of pcmcia drivers, almost
  breaks even for number of lines added vs. removed, a nice change.

  Included in here are:

   - removal of unused PCMCIA drivers (finally!)

   - Interconnect driver updates and additions

   - Lots of IIO driver updates and additions

   - MHI driver updates

   - Coresight driver updates

   - NVMEM driver updates, which required some OF updates

   - W1 driver updates and a new maintainer to manage the subsystem

   - FPGA driver updates

   - New driver subsystem, CDX, for AMD systems

   - lots of other small driver updates and additions

  All of these have been in linux-next for a while with no reported
  issues"

* tag 'char-misc-6.4-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc: (196 commits)
  mcb-lpc: Reallocate memory region to avoid memory overlapping
  mcb-pci: Reallocate memory region to avoid memory overlapping
  mcb: Return actual parsed size when reading chameleon table
  kernel/configs: Drop Android config fragments
  virt: acrn: Replace obsolete memalign() with posix_memalign()
  spmi: Add a check for remove callback when removing a SPMI driver
  spmi: fix W=1 kernel-doc warnings
  spmi: mtk-pmif: Drop of_match_ptr for ID table
  spmi: pmic-arb: Convert to platform remove callback returning void
  spmi: mtk-pmif: Convert to platform remove callback returning void
  spmi: hisi-spmi-controller: Convert to platform remove callback returning void
  w1: gpio: remove unnecessary ENOMEM messages
  w1: omap-hdq: remove unnecessary ENOMEM messages
  w1: omap-hdq: add SPDX tag
  w1: omap-hdq: allow compile testing
  w1: matrox: remove unnecessary ENOMEM messages
  w1: matrox: use inline over __inline__
  w1: matrox: switch from asm to linux header
  w1: ds2482: do not use assignment in if condition
  w1: ds2482: drop unnecessary header
  ...
parents 556eb8b7 2025b2ca
...@@ -3475,6 +3475,11 @@ D: several improvements to system programs ...@@ -3475,6 +3475,11 @@ D: several improvements to system programs
S: Oldenburg S: Oldenburg
S: Germany S: Germany
N: Mathieu Poirier
E: mathieu.poirier@linaro.org
D: CoreSight kernel subsystem, Maintainer 2014-2022
D: Perf tool support for CoreSight
N: Robert Schwebel N: Robert Schwebel
E: robert@schwebel.de E: robert@schwebel.de
W: https://www.schwebel.de W: https://www.schwebel.de
......
What: /sys/bus/cdx/rescan
Date: March 2023
Contact: nipun.gupta@amd.com
Description:
Writing y/1/on to this file will cause rescan of the bus
and devices on the CDX bus. Any new devices are scanned and
added to the list of Linux devices and any devices removed are
also deleted from Linux.
For example::
# echo 1 > /sys/bus/cdx/rescan
What: /sys/bus/cdx/devices/.../vendor
Date: March 2023
Contact: nipun.gupta@amd.com
Description:
Vendor ID for this CDX device, in hexadecimal. Vendor ID is
16 bit identifier which is specific to the device manufacturer.
Combination of Vendor ID and Device ID identifies a device.
What: /sys/bus/cdx/devices/.../device
Date: March 2023
Contact: nipun.gupta@amd.com
Description:
Device ID for this CDX device, in hexadecimal. Device ID is
16 bit identifier to identify a device type within the range
of a device manufacturer.
Combination of Vendor ID and Device ID identifies a device.
What: /sys/bus/cdx/devices/.../reset
Date: March 2023
Contact: nipun.gupta@amd.com
Description:
Writing y/1/on to this file resets the CDX device.
On resetting the device, the corresponding driver is notified
twice, once before the device is being reset, and again after
the reset has been complete.
For example::
# echo 1 > /sys/bus/cdx/.../reset
What: /sys/bus/cdx/devices/.../remove
Date: March 2023
Contact: tarak.reddy@amd.com
Description:
Writing y/1/on to this file removes the corresponding
device from the CDX bus. If the device is to be reconfigured
reconfigured in the Hardware, the device can be removed, so
that the device driver does not access the device while it is
being reconfigured.
For example::
# echo 1 > /sys/bus/cdx/devices/.../remove
...@@ -1807,8 +1807,8 @@ What: /sys/bus/iio/devices/iio:deviceX/out_resistanceX_raw ...@@ -1807,8 +1807,8 @@ What: /sys/bus/iio/devices/iio:deviceX/out_resistanceX_raw
KernelVersion: 4.3 KernelVersion: 4.3
Contact: linux-iio@vger.kernel.org Contact: linux-iio@vger.kernel.org
Description: Description:
Raw (unscaled no offset etc.) resistance reading that can be processed Raw (unscaled no offset etc.) resistance reading.
into an ohm value. Units after application of scale and offset are ohms.
What: /sys/bus/iio/devices/iio:deviceX/heater_enable What: /sys/bus/iio/devices/iio:deviceX/heater_enable
KernelVersion: 4.1.0 KernelVersion: 4.1.0
...@@ -1894,8 +1894,9 @@ What: /sys/bus/iio/devices/iio:deviceX/in_electricalconductivity_raw ...@@ -1894,8 +1894,9 @@ What: /sys/bus/iio/devices/iio:deviceX/in_electricalconductivity_raw
KernelVersion: 4.8 KernelVersion: 4.8
Contact: linux-iio@vger.kernel.org Contact: linux-iio@vger.kernel.org
Description: Description:
Raw (unscaled no offset etc.) electric conductivity reading that Raw (unscaled no offset etc.) electric conductivity reading.
can be processed to siemens per meter. Units after application of scale and offset are siemens per
meter.
What: /sys/bus/iio/devices/iio:deviceX/in_countY_raw What: /sys/bus/iio/devices/iio:deviceX/in_countY_raw
KernelVersion: 4.10 KernelVersion: 4.10
...@@ -1951,8 +1952,8 @@ What: /sys/bus/iio/devices/iio:deviceX/in_phaseY_raw ...@@ -1951,8 +1952,8 @@ What: /sys/bus/iio/devices/iio:deviceX/in_phaseY_raw
KernelVersion: 4.18 KernelVersion: 4.18
Contact: linux-iio@vger.kernel.org Contact: linux-iio@vger.kernel.org
Description: Description:
Raw (unscaled) phase difference reading from channel Y Raw (unscaled) phase difference reading from channel Y.
that can be processed to radians. Units after application of scale and offset are radians.
What: /sys/bus/iio/devices/iio:deviceX/in_massconcentration_pm1_input What: /sys/bus/iio/devices/iio:deviceX/in_massconcentration_pm1_input
What: /sys/bus/iio/devices/iio:deviceX/in_massconcentrationY_pm1_input What: /sys/bus/iio/devices/iio:deviceX/in_massconcentrationY_pm1_input
......
...@@ -234,8 +234,8 @@ Description: ...@@ -234,8 +234,8 @@ Description:
For details, see section `5.10 RAS Internal Error Register Definitions, For details, see section `5.10 RAS Internal Error Register Definitions,
Altra Family Soc BMC Interface Specification`. Altra Family Soc BMC Interface Specification`.
What: /sys/bus/platform/devices/smpro-errmon.*/event_[vrd_warn_fault|vrd_hot|dimm_hot] What: /sys/bus/platform/devices/smpro-errmon.*/event_[vrd_warn_fault|vrd_hot|dimm_hot|dimm_2x_refresh]
KernelVersion: 6.1 KernelVersion: 6.1 (event_[vrd_warn_fault|vrd_hot|dimm_hot]), 6.4 (event_dimm_2x_refresh)
Contact: Quan Nguyen <quan@os.amperecomputing.com> Contact: Quan Nguyen <quan@os.amperecomputing.com>
Description: Description:
(RO) Contains the detail information in case of VRD/DIMM warning/hot events (RO) Contains the detail information in case of VRD/DIMM warning/hot events
...@@ -258,8 +258,21 @@ Description: ...@@ -258,8 +258,21 @@ Description:
+---------------+---------------------------------------------------------------+---------------------+ +---------------+---------------------------------------------------------------+---------------------+
| DIMM HOT | /sys/bus/platform/devices/smpro-errmon.*/event_dimm_hot | DIMM Hot | | DIMM HOT | /sys/bus/platform/devices/smpro-errmon.*/event_dimm_hot | DIMM Hot |
+---------------+---------------------------------------------------------------+---------------------+ +---------------+---------------------------------------------------------------+---------------------+
| DIMM 2X | /sys/bus/platform/devices/smpro-errmon.*/event_dimm_2x_refresh| DIMM 2x refresh rate|
| REFRESH RATE | | event in high temp |
+---------------+---------------------------------------------------------------+---------------------+
For more details, see section `5.7 GPI Status Registers and 5.9 Memory Error Register Definitions,
Altra Family Soc BMC Interface Specification`.
What: /sys/bus/platform/devices/smpro-errmon.*/event_dimm[0-15]_syndrome
KernelVersion: 6.4
Contact: Quan Nguyen <quan@os.amperecomputing.com>
Description:
(RO) The sysfs returns the 2-byte DIMM failure syndrome data for slot
0-15 if it failed to initialize.
For more details, see section `5.7 GPI Status Registers, For more details, see section `5.11 Boot Stage Register Definitions,
Altra Family Soc BMC Interface Specification`. Altra Family Soc BMC Interface Specification`.
What: /sys/bus/platform/devices/smpro-misc.*/boot_progress What: /sys/bus/platform/devices/smpro-misc.*/boot_progress
......
What: /sys/bus/platform/drivers/zynqmp_fpga_manager/firmware:zynqmp-firmware:pcap/status
Date: February 2023
KernelVersion: 6.4
Contact: Nava kishore Manne <nava.kishore.manne@amd.com>
Description: (RO) Read fpga status.
Read returns a hexadecimal value that tells the current status
of the FPGA device. Each bit position in the status value is
described Below(see ug570 chapter 9).
https://docs.xilinx.com/v/u/en-US/ug570-ultrascale-configuration
====================== ==============================================
BIT(0) 0: No CRC error
1: CRC error
BIT(1) 0: Decryptor security not set
1: Decryptor security set
BIT(2) 0: MMCMs/PLLs are not locked
1: MMCMs/PLLs are locked
BIT(3) 0: DCI not matched
1: DCI matched
BIT(4) 0: Start-up sequence has not finished
1: Start-up sequence has finished
BIT(5) 0: All I/Os are placed in High-Z state
1: All I/Os behave as configured
BIT(6) 0: Flip-flops and block RAM are write disabled
1: Flip-flops and block RAM are write enabled
BIT(7) 0: GHIGH_B_STATUS asserted
1: GHIGH_B_STATUS deasserted
BIT(8) to BIT(10) Status of the mode pins
BIT(11) 0: Initialization has not finished
1: Initialization finished
BIT(12) Value on INIT_B_PIN pin
BIT(13) 0: Signal not released
1: Signal released
BIT(14) Value on DONE_PIN pin.
BIT(15) 0: No IDCODE_ERROR
1: IDCODE_ERROR
BIT(16) 0: No SECURITY_ERROR
1: SECURITY_ERROR
BIT(17) System Monitor over-temperature if set
BIT(18) to BIT(20) Start-up state machine (0 to 7)
Phase 0 = 000
Phase 1 = 001
Phase 2 = 011
Phase 3 = 010
Phase 4 = 110
Phase 5 = 111
Phase 6 = 101
Phase 7 = 100
BIT(25) to BIT(26) Indicates the detected bus width
00 = x1
01 = x8
10 = x16
11 = x32
====================== ==============================================
The other bits are reserved.
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/bus/xlnx,versal-net-cdx.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: AMD CDX bus controller
description: |
CDX bus controller for AMD devices is implemented to dynamically
detect CDX bus and devices using the firmware.
The CDX bus manages multiple FPGA based hardware devices, which
can support network, crypto or any other specialized type of
devices. These FPGA based devices can be added/modified dynamically
on run-time.
All devices on the CDX bus will have a unique streamid (for IOMMU)
and a unique device ID (for MSI) corresponding to a requestor ID
(one to one associated with the device). The streamid and deviceid
are used to configure SMMU and GIC-ITS respectively.
iommu-map property is used to define the set of stream ids
corresponding to each device and the associated IOMMU.
The MSI writes are accompanied by sideband data (Device ID).
The msi-map property is used to associate the devices with the
device ID as well as the associated ITS controller.
rproc property (xlnx,rproc) is used to identify the remote processor
with which APU (Application Processor Unit) interacts to find out
the bus and device configuration.
maintainers:
- Nipun Gupta <nipun.gupta@amd.com>
- Nikhil Agarwal <nikhil.agarwal@amd.com>
properties:
compatible:
const: xlnx,versal-net-cdx
iommu-map: true
msi-map: true
xlnx,rproc:
$ref: /schemas/types.yaml#/definitions/phandle
description:
phandle to the remoteproc_r5 rproc node using which APU interacts
with remote processor.
ranges: true
"#address-cells":
enum: [1, 2]
"#size-cells":
enum: [1, 2]
required:
- compatible
- iommu-map
- msi-map
- xlnx,rproc
- ranges
- "#address-cells"
- "#size-cells"
additionalProperties: false
examples:
- |
cdx {
compatible = "xlnx,versal-net-cdx";
#address-cells = <1>;
#size-cells = <1>;
/* define map for RIDs 250-259 */
iommu-map = <250 &smmu 250 10>;
/* define msi map for RIDs 250-259 */
msi-map = <250 &its 250 10>;
xlnx,rproc = <&remoteproc_r5>;
ranges;
};
...@@ -34,9 +34,11 @@ properties: ...@@ -34,9 +34,11 @@ properties:
clock-names: clock-names:
const: fck const: fck
power-domains: true power-domains:
maxItems: 1
resets: true resets:
maxItems: 1
"#address-cells": "#address-cells":
const: 1 const: 1
...@@ -51,6 +53,8 @@ required: ...@@ -51,6 +53,8 @@ required:
- reg - reg
- clocks - clocks
- clock-names - clock-names
- power-domains
- resets
- "#address-cells" - "#address-cells"
- "#size-cells" - "#size-cells"
...@@ -108,21 +112,16 @@ patternProperties: ...@@ -108,21 +112,16 @@ patternProperties:
examples: examples:
- | - |
#include <dt-bindings/clock/r8a7791-clock.h> #include <dt-bindings/clock/r8a7791-cpg-mssr.h>
#include <dt-bindings/power/r8a7791-sysc.h> #include <dt-bindings/power/r8a7791-sysc.h>
soc {
#address-cells = <2>;
#size-cells = <2>;
adc@e6e54000 { adc@e6e54000 {
compatible = "renesas,r8a7791-gyroadc", "renesas,rcar-gyroadc"; compatible = "renesas,r8a7791-gyroadc", "renesas,rcar-gyroadc";
reg = <0 0xe6e54000 0 64>; reg = <0xe6e54000 64>;
clocks = <&mstp9_clks R8A7791_CLK_GYROADC>; clocks = <&cpg CPG_MOD 901>;
clock-names = "fck"; clock-names = "fck";
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
resets = <&cpg 901>;
pinctrl-0 = <&adc_pins>;
pinctrl-names = "default";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
...@@ -139,5 +138,4 @@ examples: ...@@ -139,5 +138,4 @@ examples:
vref-supply = <&vref_max1162>; vref-supply = <&vref_max1162>;
}; };
}; };
};
... ...
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/iio/adc/ti,ads1100.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: TI ADS1100/ADS1000 single channel I2C analog to digital converter
maintainers:
- Mike Looijmans <mike.looijmans@topic.nl>
description: |
Datasheet at: https://www.ti.com/lit/gpn/ads1100
properties:
compatible:
enum:
- ti,ads1100
- ti,ads1000
reg:
maxItems: 1
vdd-supply: true
"#io-channel-cells":
const: 0
required:
- compatible
- reg
additionalProperties: false
examples:
- |
i2c {
#address-cells = <1>;
#size-cells = <0>;
adc@49 {
compatible = "ti,ads1100";
reg = <0x49>;
};
};
...
...@@ -101,6 +101,15 @@ patternProperties: ...@@ -101,6 +101,15 @@ patternProperties:
When not configured as a comparator, the GPO will be treated as an When not configured as a comparator, the GPO will be treated as an
output-only GPIO. output-only GPIO.
drive-strength-microamp:
description: |
For channels configured as digital input, this configures the sink
current.
minimum: 0
maximum: 1800
default: 0
multipleOf: 120
required: required:
- reg - reg
......
...@@ -46,6 +46,9 @@ properties: ...@@ -46,6 +46,9 @@ properties:
- items: - items:
- const: st,ism330is - const: st,ism330is
- const: st,lsm6dso16is - const: st,lsm6dso16is
- items:
- const: st,asm330lhb
- const: st,asm330lhh
reg: reg:
maxItems: 1 maxItems: 1
......
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/iio/light/rohm,bu27034.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ROHM BU27034 ambient light sensor
maintainers:
- Matti Vaittinen <mazziesaccount@gmail.com>
description: |
ROHM BU27034 is an ambient light sesnor with 3 channels and 3 photo diodes
capable of detecting a very wide range of illuminance. Typical application
is adjusting LCD and backlight power of TVs and mobile phones.
https://fscdn.rohm.com/en/products/databook/datasheet/ic/sensor/light/bu27034nuc-e.pdf
properties:
compatible:
const: rohm,bu27034
reg:
maxItems: 1
vdd-supply: true
required:
- compatible
- reg
additionalProperties: false
examples:
- |
i2c {
#address-cells = <1>;
#size-cells = <0>;
light-sensor@38 {
compatible = "rohm,bu27034";
reg = <0x38>;
vdd-supply = <&vdd>;
};
};
...
...@@ -17,6 +17,7 @@ description: | ...@@ -17,6 +17,7 @@ description: |
https://www.bosch-sensortec.com/bst/products/all_products/bmp280 https://www.bosch-sensortec.com/bst/products/all_products/bmp280
https://www.bosch-sensortec.com/bst/products/all_products/bme280 https://www.bosch-sensortec.com/bst/products/all_products/bme280
https://www.bosch-sensortec.com/bst/products/all_products/bmp380 https://www.bosch-sensortec.com/bst/products/all_products/bmp380
https://www.bosch-sensortec.com/bst/products/all_products/bmp580
properties: properties:
compatible: compatible:
...@@ -26,6 +27,7 @@ properties: ...@@ -26,6 +27,7 @@ properties:
- bosch,bmp280 - bosch,bmp280
- bosch,bme280 - bosch,bme280
- bosch,bmp380 - bosch,bmp380
- bosch,bmp580
reg: reg:
maxItems: 1 maxItems: 1
......
...@@ -11,9 +11,6 @@ description: The STMicroelectronics sensor devices are pretty straight-forward ...@@ -11,9 +11,6 @@ description: The STMicroelectronics sensor devices are pretty straight-forward
what type of sensor it is. what type of sensor it is.
Note that whilst this covers many STMicro MEMs sensors, some more complex Note that whilst this covers many STMicro MEMs sensors, some more complex
IMUs need their own bindings. IMUs need their own bindings.
The STMicroelectronics sensor devices are pretty straight-forward I2C or
SPI devices, all sharing the same device tree descriptions no matter what
type of sensor it is.
maintainers: maintainers:
- Denis Ciocca <denis.ciocca@st.com> - Denis Ciocca <denis.ciocca@st.com>
...@@ -48,6 +45,9 @@ properties: ...@@ -48,6 +45,9 @@ properties:
- st,lsm330d-accel - st,lsm330d-accel
- st,lsm330dl-accel - st,lsm330dl-accel
- st,lsm330dlc-accel - st,lsm330dlc-accel
- items:
- const: st,iis328dq
- const: st,h3lis331dl-accel
- description: Silan Accelerometers - description: Silan Accelerometers
enum: enum:
- silan,sc7a20 - silan,sc7a20
......
...@@ -18,6 +18,28 @@ description: | ...@@ -18,6 +18,28 @@ description: |
https://www.analog.com/media/en/technical-documentation/data-sheets/29861fa.pdf https://www.analog.com/media/en/technical-documentation/data-sheets/29861fa.pdf
https://www.analog.com/media/en/technical-documentation/data-sheets/ltm2985.pdf https://www.analog.com/media/en/technical-documentation/data-sheets/ltm2985.pdf
$defs:
sensor-node:
type: object
description: Sensor node common constraints
properties:
reg:
description:
Channel number. Connects the sensor to the channel with this number
of the device.
minimum: 1
maximum: 20
adi,sensor-type:
description: Type of sensor connected to the device.
$ref: /schemas/types.yaml#/definitions/uint32
required:
- reg
- adi,sensor-type
properties: properties:
compatible: compatible:
oneOf: oneOf:
...@@ -64,28 +86,10 @@ properties: ...@@ -64,28 +86,10 @@ properties:
const: 0 const: 0
patternProperties: patternProperties:
"@([0-9a-f]+)$":
type: object
description: Sensor.
properties:
reg:
description:
Channel number. Connects the sensor to the channel with this number
of the device.
minimum: 1
maximum: 20
adi,sensor-type:
description: Type of sensor connected to the device.
$ref: /schemas/types.yaml#/definitions/uint32
required:
- reg
- adi,sensor-type
"^thermocouple@": "^thermocouple@":
type: object $ref: '#/$defs/sensor-node'
unevaluatedProperties: false
description: Thermocouple sensor. description: Thermocouple sensor.
properties: properties:
...@@ -123,7 +127,7 @@ patternProperties: ...@@ -123,7 +127,7 @@ patternProperties:
description: description:
Used for digitizing custom thermocouples. Used for digitizing custom thermocouples.
See Page 59 of the datasheet. See Page 59 of the datasheet.
$ref: /schemas/types.yaml#/definitions/uint64-matrix $ref: /schemas/types.yaml#/definitions/int64-matrix
minItems: 3 minItems: 3
maxItems: 64 maxItems: 64
items: items:
...@@ -141,7 +145,9 @@ patternProperties: ...@@ -141,7 +145,9 @@ patternProperties:
- adi,custom-thermocouple - adi,custom-thermocouple
"^diode@": "^diode@":
type: object $ref: '#/$defs/sensor-node'
unevaluatedProperties: false
description: Diode sensor. description: Diode sensor.
properties: properties:
...@@ -184,7 +190,8 @@ patternProperties: ...@@ -184,7 +190,8 @@ patternProperties:
default: 0 default: 0
"^rtd@": "^rtd@":
type: object $ref: '#/$defs/sensor-node'
unevaluatedProperties: false
description: RTD sensor. description: RTD sensor.
properties: properties:
...@@ -282,7 +289,8 @@ patternProperties: ...@@ -282,7 +289,8 @@ patternProperties:
- adi,custom-rtd - adi,custom-rtd
"^thermistor@": "^thermistor@":
type: object $ref: '#/$defs/sensor-node'
unevaluatedProperties: false
description: Thermistor sensor. description: Thermistor sensor.
properties: properties:
...@@ -383,7 +391,8 @@ patternProperties: ...@@ -383,7 +391,8 @@ patternProperties:
- adi,custom-thermistor - adi,custom-thermistor
"^adc@": "^adc@":
type: object $ref: '#/$defs/sensor-node'
unevaluatedProperties: false
description: Direct ADC sensor. description: Direct ADC sensor.
properties: properties:
...@@ -397,7 +406,8 @@ patternProperties: ...@@ -397,7 +406,8 @@ patternProperties:
type: boolean type: boolean
"^temp@": "^temp@":
type: object $ref: '#/$defs/sensor-node'
unevaluatedProperties: false
description: Active analog temperature sensor. description: Active analog temperature sensor.
properties: properties:
...@@ -426,7 +436,8 @@ patternProperties: ...@@ -426,7 +436,8 @@ patternProperties:
- adi,custom-temp - adi,custom-temp
"^rsense@": "^rsense@":
type: object $ref: '#/$defs/sensor-node'
unevaluatedProperties: false
description: Sense resistor sensor. description: Sense resistor sensor.
properties: properties:
......
...@@ -7,9 +7,10 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# ...@@ -7,9 +7,10 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: TI TMP117 - Digital temperature sensor with integrated NV memory title: TI TMP117 - Digital temperature sensor with integrated NV memory
description: | description: |
TI TMP117 - Digital temperature sensor with integrated NV memory that supports TI TMP116/117 - Digital temperature sensor with integrated NV memory that
I2C interface. supports I2C interface.
https://www.ti.com/lit/gpn/tmp1 https://www.ti.com/lit/gpn/tmp116
https://www.ti.com/lit/gpn/tmp117
maintainers: maintainers:
- Puranjay Mohan <puranjay12@gmail.com> - Puranjay Mohan <puranjay12@gmail.com>
...@@ -17,6 +18,7 @@ maintainers: ...@@ -17,6 +18,7 @@ maintainers:
properties: properties:
compatible: compatible:
enum: enum:
- ti,tmp116
- ti,tmp117 - ti,tmp117
reg: reg:
......
...@@ -22,14 +22,14 @@ description: | ...@@ -22,14 +22,14 @@ description: |
properties: properties:
compatible: compatible:
oneOf: oneOf:
- const: qcom,msm8998-bwmon # BWMON v4
- items: - items:
- enum: - enum:
- qcom,sc7280-cpu-bwmon - qcom,sc7280-cpu-bwmon
- qcom,sc8280xp-cpu-bwmon - qcom,sc8280xp-cpu-bwmon
- qcom,sdm845-bwmon - qcom,sdm845-cpu-bwmon
- qcom,sm8550-cpu-bwmon - qcom,sm8550-cpu-bwmon
- const: qcom,msm8998-bwmon - const: qcom,sdm845-bwmon # BWMON v4, unified register space
- const: qcom,msm8998-bwmon # BWMON v4
- items: - items:
- enum: - enum:
- qcom,sc8280xp-llcc-bwmon - qcom,sc8280xp-llcc-bwmon
...@@ -49,9 +49,13 @@ properties: ...@@ -49,9 +49,13 @@ properties:
type: object type: object
reg: reg:
# BWMON v4 (currently described) and BWMON v5 use one register address # BWMON v5 uses one register address space, v1-v4 use one or two.
# space. BWMON v2 uses two register spaces - not yet described. minItems: 1
maxItems: 1 maxItems: 2
reg-names:
minItems: 1
maxItems: 2
required: required:
- compatible - compatible
...@@ -63,13 +67,36 @@ required: ...@@ -63,13 +67,36 @@ required:
additionalProperties: false additionalProperties: false
allOf:
- if:
properties:
compatible:
const: qcom,msm8998-bwmon
then:
properties:
reg:
minItems: 2
reg-names:
items:
- const: monitor
- const: global
else:
properties:
reg:
maxItems: 1
reg-names:
maxItems: 1
examples: examples:
- | - |
#include <dt-bindings/interconnect/qcom,sdm845.h> #include <dt-bindings/interconnect/qcom,sdm845.h>
#include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/arm-gic.h>
pmu@1436400 { pmu@1436400 {
compatible = "qcom,sdm845-bwmon", "qcom,msm8998-bwmon"; compatible = "qcom,sdm845-cpu-bwmon", "qcom,sdm845-bwmon";
reg = <0x01436400 0x600>; reg = <0x01436400 0x600>;
interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_LLCC 3>; interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_LLCC 3>;
......
...@@ -29,6 +29,7 @@ properties: ...@@ -29,6 +29,7 @@ properties:
- enum: - enum:
- qcom,sc7280-epss-l3 - qcom,sc7280-epss-l3
- qcom,sc8280xp-epss-l3 - qcom,sc8280xp-epss-l3
- qcom,sm6375-cpucp-l3
- qcom,sm8250-epss-l3 - qcom,sm8250-epss-l3
- qcom,sm8350-epss-l3 - qcom,sm8350-epss-l3
- const: qcom,epss-l3 - const: qcom,epss-l3
......
...@@ -11,7 +11,7 @@ maintainers: ...@@ -11,7 +11,7 @@ maintainers:
- Maxime Ripard <mripard@kernel.org> - Maxime Ripard <mripard@kernel.org>
allOf: allOf:
- $ref: "nvmem.yaml#" - $ref: nvmem.yaml#
properties: properties:
compatible: compatible:
......
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/nvmem/amlogic,meson-gxbb-efuse.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Amlogic Meson GX eFuse
maintainers:
- Neil Armstrong <neil.armstrong@linaro.org>
allOf:
- $ref: nvmem.yaml#
properties:
compatible:
oneOf:
- const: amlogic,meson-gxbb-efuse
- items:
- const: amlogic,meson-gx-efuse
- const: amlogic,meson-gxbb-efuse
clocks:
maxItems: 1
secure-monitor:
description: phandle to the secure-monitor node
$ref: /schemas/types.yaml#/definitions/phandle
required:
- compatible
- clocks
- secure-monitor
unevaluatedProperties: false
examples:
- |
efuse: efuse {
compatible = "amlogic,meson-gxbb-efuse";
clocks = <&clk_efuse>;
#address-cells = <1>;
#size-cells = <1>;
secure-monitor = <&sm>;
sn: sn@14 {
reg = <0x14 0x10>;
};
eth_mac: mac@34 {
reg = <0x34 0x10>;
};
bid: bid@46 {
reg = <0x46 0x30>;
};
};
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/nvmem/amlogic,meson6-efuse.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Amlogic Meson6 eFuse
maintainers:
- Neil Armstrong <neil.armstrong@linaro.org>
- Martin Blumenstingl <martin.blumenstingl@googlemail.com>
allOf:
- $ref: nvmem.yaml#
properties:
compatible:
enum:
- amlogic,meson6-efuse
- amlogic,meson8-efuse
- amlogic,meson8b-efuse
reg:
maxItems: 1
clocks:
maxItems: 1
clock-names:
const: core
required:
- compatible
- reg
- clocks
- clock-names
unevaluatedProperties: false
examples:
- |
efuse: efuse@0 {
compatible = "amlogic,meson6-efuse";
reg = <0x0 0x2000>;
clocks = <&clk_efuse>;
clock-names = "core";
#address-cells = <1>;
#size-cells = <1>;
ethernet_mac_address: mac@1b4 {
reg = <0x1b4 0x6>;
};
temperature_calib: calib@1f4 {
reg = <0x1f4 0x4>;
};
};
= Amlogic Meson GX eFuse device tree bindings =
Required properties:
- compatible: should be "amlogic,meson-gxbb-efuse"
- clocks: phandle to the efuse peripheral clock provided by the
clock controller.
- secure-monitor: phandle to the secure-monitor node
= Data cells =
Are child nodes of eFuse, bindings of which as described in
bindings/nvmem/nvmem.txt
Example:
efuse: efuse {
compatible = "amlogic,meson-gxbb-efuse";
clocks = <&clkc CLKID_EFUSE>;
#address-cells = <1>;
#size-cells = <1>;
secure-monitor = <&sm>;
sn: sn@14 {
reg = <0x14 0x10>;
};
eth_mac: eth_mac@34 {
reg = <0x34 0x10>;
};
bid: bid@46 {
reg = <0x46 0x30>;
};
};
sm: secure-monitor {
compatible = "amlogic,meson-gxbb-sm";
};
= Data consumers =
Are device nodes which consume nvmem data cells.
For example:
eth_mac {
...
nvmem-cells = <&eth_mac>;
nvmem-cell-names = "eth_mac";
};
Amlogic Meson6/Meson8/Meson8b efuse
Required Properties:
- compatible: depending on the SoC this should be one of:
- "amlogic,meson6-efuse"
- "amlogic,meson8-efuse"
- "amlogic,meson8b-efuse"
- reg: base address and size of the efuse registers
- clocks: a reference to the efuse core gate clock
- clock-names: must be "core"
All properties and sub-nodes as well as the consumer bindings
defined in nvmem.txt in this directory are also supported.
Example:
efuse: nvmem@0 {
compatible = "amlogic,meson8-efuse";
reg = <0x0 0x2000>;
clocks = <&clkc CLKID_EFUSE>;
clock-names = "core";
};
...@@ -15,7 +15,7 @@ maintainers: ...@@ -15,7 +15,7 @@ maintainers:
- Sven Peter <sven@svenpeter.dev> - Sven Peter <sven@svenpeter.dev>
allOf: allOf:
- $ref: "nvmem.yaml#" - $ref: nvmem.yaml#
properties: properties:
compatible: compatible:
......
...@@ -20,7 +20,7 @@ maintainers: ...@@ -20,7 +20,7 @@ maintainers:
- Rafał Miłecki <rafal@milecki.pl> - Rafał Miłecki <rafal@milecki.pl>
allOf: allOf:
- $ref: "nvmem.yaml#" - $ref: nvmem.yaml#
properties: properties:
compatible: compatible:
......
...@@ -14,7 +14,7 @@ description: | ...@@ -14,7 +14,7 @@ description: |
unique identifier per part. unique identifier per part.
allOf: allOf:
- $ref: "nvmem.yaml#" - $ref: nvmem.yaml#
properties: properties:
compatible: compatible:
......
...@@ -14,7 +14,7 @@ description: | ...@@ -14,7 +14,7 @@ description: |
i.MX25, i.MX27, i.MX31, i.MX35, i.MX51 and i.MX53 SoCs. i.MX25, i.MX27, i.MX31, i.MX35, i.MX51 and i.MX53 SoCs.
allOf: allOf:
- $ref: "nvmem.yaml#" - $ref: nvmem.yaml#
properties: properties:
compatible: compatible:
......
...@@ -15,7 +15,7 @@ description: | ...@@ -15,7 +15,7 @@ description: |
i.MX7D/S, i.MX7ULP, i.MX8MQ, i.MX8MM, i.MX8MN and i.MX8MP SoCs. i.MX7D/S, i.MX7ULP, i.MX8MQ, i.MX8MM, i.MX8MN and i.MX8MP SoCs.
allOf: allOf:
- $ref: "nvmem.yaml#" - $ref: nvmem.yaml#
properties: properties:
compatible: compatible:
......
...@@ -10,7 +10,7 @@ maintainers: ...@@ -10,7 +10,7 @@ maintainers:
- PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com> - PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com>
allOf: allOf:
- $ref: "nvmem.yaml#" - $ref: nvmem.yaml#
properties: properties:
compatible: compatible:
......
...@@ -61,7 +61,7 @@ properties: ...@@ -61,7 +61,7 @@ properties:
type: object type: object
additionalProperties: false additionalProperties: false
platforn-name: platform-name:
type: object type: object
additionalProperties: false additionalProperties: false
......
...@@ -15,7 +15,7 @@ maintainers: ...@@ -15,7 +15,7 @@ maintainers:
- Lala Lin <lala.lin@mediatek.com> - Lala Lin <lala.lin@mediatek.com>
allOf: allOf:
- $ref: "nvmem.yaml#" - $ref: nvmem.yaml#
properties: properties:
$nodename: $nodename:
......
...@@ -15,7 +15,7 @@ description: | ...@@ -15,7 +15,7 @@ description: |
settings, chip identifiers) or user specific data could be stored. settings, chip identifiers) or user specific data could be stored.
allOf: allOf:
- $ref: "nvmem.yaml#" - $ref: nvmem.yaml#
properties: properties:
compatible: compatible:
......
...@@ -10,7 +10,7 @@ maintainers: ...@@ -10,7 +10,7 @@ maintainers:
- Anson Huang <Anson.Huang@nxp.com> - Anson Huang <Anson.Huang@nxp.com>
allOf: allOf:
- $ref: "nvmem.yaml#" - $ref: nvmem.yaml#
properties: properties:
compatible: compatible:
......
...@@ -17,7 +17,7 @@ maintainers: ...@@ -17,7 +17,7 @@ maintainers:
- Emmanuel Gil Peyrot <linkmauve@linkmauve.fr> - Emmanuel Gil Peyrot <linkmauve@linkmauve.fr>
allOf: allOf:
- $ref: "nvmem.yaml#" - $ref: nvmem.yaml#
properties: properties:
compatible: compatible:
......
...@@ -10,7 +10,7 @@ maintainers: ...@@ -10,7 +10,7 @@ maintainers:
- Srinivas Kandagatla <srinivas.kandagatla@linaro.org> - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
allOf: allOf:
- $ref: "nvmem.yaml#" - $ref: nvmem.yaml#
properties: properties:
compatible: compatible:
...@@ -32,6 +32,8 @@ properties: ...@@ -32,6 +32,8 @@ properties:
- qcom,sdm670-qfprom - qcom,sdm670-qfprom
- qcom,sdm845-qfprom - qcom,sdm845-qfprom
- qcom,sm6115-qfprom - qcom,sm6115-qfprom
- qcom,sm6350-qfprom
- qcom,sm6375-qfprom
- qcom,sm8150-qfprom - qcom,sm8150-qfprom
- qcom,sm8250-qfprom - qcom,sm8250-qfprom
- const: qcom,qfprom - const: qcom,qfprom
......
...@@ -15,7 +15,7 @@ description: | ...@@ -15,7 +15,7 @@ description: |
to/from the PBUS. to/from the PBUS.
allOf: allOf:
- $ref: "nvmem.yaml#" - $ref: nvmem.yaml#
properties: properties:
compatible: compatible:
...@@ -42,11 +42,15 @@ unevaluatedProperties: false ...@@ -42,11 +42,15 @@ unevaluatedProperties: false
examples: examples:
- | - |
pmic {
#address-cells = <1>;
#size-cells = <0>;
sdam_1: nvram@b000 { sdam_1: nvram@b000 {
compatible = "qcom,spmi-sdam";
reg = <0xb000>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
compatible = "qcom,spmi-sdam";
reg = <0xb000 0x100>;
ranges = <0 0xb000 0x100>; ranges = <0 0xb000 0x100>;
/* Data cells */ /* Data cells */
...@@ -55,4 +59,5 @@ examples: ...@@ -55,4 +59,5 @@ examples:
bits = <6 2>; bits = <6 2>;
}; };
}; };
};
... ...
...@@ -10,7 +10,7 @@ maintainers: ...@@ -10,7 +10,7 @@ maintainers:
- Nicolas Saenz Julienne <nsaenzjulienne@suse.de> - Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
allOf: allOf:
- $ref: "nvmem.yaml#" - $ref: nvmem.yaml#
properties: properties:
compatible: compatible:
......
...@@ -10,7 +10,7 @@ maintainers: ...@@ -10,7 +10,7 @@ maintainers:
- Heiko Stuebner <heiko@sntech.de> - Heiko Stuebner <heiko@sntech.de>
allOf: allOf:
- $ref: "nvmem.yaml#" - $ref: nvmem.yaml#
properties: properties:
compatible: compatible:
......
...@@ -11,7 +11,7 @@ maintainers: ...@@ -11,7 +11,7 @@ maintainers:
- Kunihiko Hayashi <hayashi.kunihiko@socionext.com> - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
allOf: allOf:
- $ref: "nvmem.yaml#" - $ref: nvmem.yaml#
properties: properties:
"#address-cells": true "#address-cells": true
......
...@@ -16,7 +16,7 @@ maintainers: ...@@ -16,7 +16,7 @@ maintainers:
- Fabrice Gasnier <fabrice.gasnier@foss.st.com> - Fabrice Gasnier <fabrice.gasnier@foss.st.com>
allOf: allOf:
- $ref: "nvmem.yaml#" - $ref: nvmem.yaml#
properties: properties:
compatible: compatible:
......
...@@ -11,7 +11,7 @@ maintainers: ...@@ -11,7 +11,7 @@ maintainers:
- Vincent Shih <vincent.sunplus@gmail.com> - Vincent Shih <vincent.sunplus@gmail.com>
allOf: allOf:
- $ref: "nvmem.yaml#" - $ref: nvmem.yaml#
properties: properties:
compatible: compatible:
......
...@@ -50,7 +50,11 @@ properties: ...@@ -50,7 +50,11 @@ properties:
ethaddr: ethaddr:
type: object type: object
description: Ethernet interface's MAC address description: Ethernet interfaces base MAC address.
properties:
"#nvmem-cell-cells":
description: The first argument is a MAC address offset.
const: 1
additionalProperties: false additionalProperties: false
...@@ -72,6 +76,7 @@ examples: ...@@ -72,6 +76,7 @@ examples:
reg = <0x40000 0x10000>; reg = <0x40000 0x10000>;
mac: ethaddr { mac: ethaddr {
#nvmem-cell-cells = <1>;
}; };
}; };
}; };
......
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/w1/maxim,ds2482.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Maxim One wire bus master controller
maintainers:
- Stefan Wahren <stefan.wahren@chargebyte.com>
description: |
I2C to 1-wire bridges
https://www.analog.com/media/en/technical-documentation/data-sheets/ds2482-100.pdf
https://www.analog.com/media/en/technical-documentation/data-sheets/DS2482-800.pdf
https://www.analog.com/media/en/technical-documentation/data-sheets/DS2484.pdf
properties:
compatible:
enum:
- maxim,ds2482
- maxim,ds2484
reg:
maxItems: 1
required:
- compatible
- reg
additionalProperties:
type: object
examples:
- |
i2c {
#address-cells = <1>;
#size-cells = <0>;
onewire@18 {
compatible = "maxim,ds2484";
reg = <0x18>;
};
};
...@@ -185,3 +185,18 @@ ex:: ...@@ -185,3 +185,18 @@ ex::
===================== =====================
See Documentation/devicetree/bindings/nvmem/nvmem.txt See Documentation/devicetree/bindings/nvmem/nvmem.txt
8. NVMEM layouts
================
NVMEM layouts are yet another mechanism to create cells. With the device
tree binding it is possible to specify simple cells by using an offset
and a length. Sometimes, the cells doesn't have a static offset, but
the content is still well defined, e.g. tag-length-values. In this case,
the NVMEM device content has to be first parsed and the cells need to
be added accordingly. Layouts let you read the content of the NVMEM device
and let you add cells dynamically.
Another use case for layouts is the post processing of cells. With layouts,
it is possible to associate a custom post processing hook to a cell. It
even possible to add this hook to cells not created by the layout itself.
...@@ -72,7 +72,6 @@ PG_MAGIC 'P' pg_{read,write}_hdr ``include/linux/ ...@@ -72,7 +72,6 @@ PG_MAGIC 'P' pg_{read,write}_hdr ``include/linux/
APM_BIOS_MAGIC 0x4101 apm_user ``arch/x86/kernel/apm_32.c`` APM_BIOS_MAGIC 0x4101 apm_user ``arch/x86/kernel/apm_32.c``
FASYNC_MAGIC 0x4601 fasync_struct ``include/linux/fs.h`` FASYNC_MAGIC 0x4601 fasync_struct ``include/linux/fs.h``
SLIP_MAGIC 0x5302 slip ``drivers/net/slip.h`` SLIP_MAGIC 0x5302 slip ``drivers/net/slip.h``
MGSLPC_MAGIC 0x5402 mgslpc_info ``drivers/char/pcmcia/synclink_cs.c``
BAYCOM_MAGIC 0x19730510 baycom_state ``drivers/net/baycom_epp.c`` BAYCOM_MAGIC 0x19730510 baycom_state ``drivers/net/baycom_epp.c``
HDLCDRV_MAGIC 0x5ac6e778 hdlcdrv_state ``include/linux/hdlcdrv.h`` HDLCDRV_MAGIC 0x5ac6e778 hdlcdrv_state ``include/linux/hdlcdrv.h``
KV_MAGIC 0x5f4b565f kernel_vars_s ``arch/mips/include/asm/sn/klkernvars.h`` KV_MAGIC 0x5f4b565f kernel_vars_s ``arch/mips/include/asm/sn/klkernvars.h``
......
...@@ -78,7 +78,6 @@ PG_MAGIC 'P' pg_{read,write}_hdr ``include/linux/ ...@@ -78,7 +78,6 @@ PG_MAGIC 'P' pg_{read,write}_hdr ``include/linux/
APM_BIOS_MAGIC 0x4101 apm_user ``arch/x86/kernel/apm_32.c`` APM_BIOS_MAGIC 0x4101 apm_user ``arch/x86/kernel/apm_32.c``
FASYNC_MAGIC 0x4601 fasync_struct ``include/linux/fs.h`` FASYNC_MAGIC 0x4601 fasync_struct ``include/linux/fs.h``
SLIP_MAGIC 0x5302 slip ``drivers/net/slip.h`` SLIP_MAGIC 0x5302 slip ``drivers/net/slip.h``
MGSLPC_MAGIC 0x5402 mgslpc_info ``drivers/char/pcmcia/synclink_cs.c``
BAYCOM_MAGIC 0x19730510 baycom_state ``drivers/net/baycom_epp.c`` BAYCOM_MAGIC 0x19730510 baycom_state ``drivers/net/baycom_epp.c``
HDLCDRV_MAGIC 0x5ac6e778 hdlcdrv_state ``include/linux/hdlcdrv.h`` HDLCDRV_MAGIC 0x5ac6e778 hdlcdrv_state ``include/linux/hdlcdrv.h``
KV_MAGIC 0x5f4b565f kernel_vars_s ``arch/mips/include/asm/sn/klkernvars.h`` KV_MAGIC 0x5f4b565f kernel_vars_s ``arch/mips/include/asm/sn/klkernvars.h``
......
...@@ -77,7 +77,6 @@ PG_MAGIC 'P' pg_{read,write}_hdr ``include/linux/ ...@@ -77,7 +77,6 @@ PG_MAGIC 'P' pg_{read,write}_hdr ``include/linux/
APM_BIOS_MAGIC 0x4101 apm_user ``arch/x86/kernel/apm_32.c`` APM_BIOS_MAGIC 0x4101 apm_user ``arch/x86/kernel/apm_32.c``
FASYNC_MAGIC 0x4601 fasync_struct ``include/linux/fs.h`` FASYNC_MAGIC 0x4601 fasync_struct ``include/linux/fs.h``
SLIP_MAGIC 0x5302 slip ``drivers/net/slip.h`` SLIP_MAGIC 0x5302 slip ``drivers/net/slip.h``
MGSLPC_MAGIC 0x5402 mgslpc_info ``drivers/char/pcmcia/synclink_cs.c``
BAYCOM_MAGIC 0x19730510 baycom_state ``drivers/net/baycom_epp.c`` BAYCOM_MAGIC 0x19730510 baycom_state ``drivers/net/baycom_epp.c``
HDLCDRV_MAGIC 0x5ac6e778 hdlcdrv_state ``include/linux/hdlcdrv.h`` HDLCDRV_MAGIC 0x5ac6e778 hdlcdrv_state ``include/linux/hdlcdrv.h``
KV_MAGIC 0x5f4b565f kernel_vars_s ``arch/mips/include/asm/sn/klkernvars.h`` KV_MAGIC 0x5f4b565f kernel_vars_s ``arch/mips/include/asm/sn/klkernvars.h``
......
...@@ -61,7 +61,6 @@ PG_MAGIC 'P' pg_{read,write}_hdr ``include/linux/ ...@@ -61,7 +61,6 @@ PG_MAGIC 'P' pg_{read,write}_hdr ``include/linux/
APM_BIOS_MAGIC 0x4101 apm_user ``arch/x86/kernel/apm_32.c`` APM_BIOS_MAGIC 0x4101 apm_user ``arch/x86/kernel/apm_32.c``
FASYNC_MAGIC 0x4601 fasync_struct ``include/linux/fs.h`` FASYNC_MAGIC 0x4601 fasync_struct ``include/linux/fs.h``
SLIP_MAGIC 0x5302 slip ``drivers/net/slip.h`` SLIP_MAGIC 0x5302 slip ``drivers/net/slip.h``
MGSLPC_MAGIC 0x5402 mgslpc_info ``drivers/char/pcmcia/synclink_cs.c``
BAYCOM_MAGIC 0x19730510 baycom_state ``drivers/net/baycom_epp.c`` BAYCOM_MAGIC 0x19730510 baycom_state ``drivers/net/baycom_epp.c``
HDLCDRV_MAGIC 0x5ac6e778 hdlcdrv_state ``include/linux/hdlcdrv.h`` HDLCDRV_MAGIC 0x5ac6e778 hdlcdrv_state ``include/linux/hdlcdrv.h``
KV_MAGIC 0x5f4b565f kernel_vars_s ``arch/mips/include/asm/sn/klkernvars.h`` KV_MAGIC 0x5f4b565f kernel_vars_s ``arch/mips/include/asm/sn/klkernvars.h``
......
...@@ -64,7 +64,6 @@ PG_MAGIC 'P' pg_{read,write}_hdr ``include/linux/ ...@@ -64,7 +64,6 @@ PG_MAGIC 'P' pg_{read,write}_hdr ``include/linux/
APM_BIOS_MAGIC 0x4101 apm_user ``arch/x86/kernel/apm_32.c`` APM_BIOS_MAGIC 0x4101 apm_user ``arch/x86/kernel/apm_32.c``
FASYNC_MAGIC 0x4601 fasync_struct ``include/linux/fs.h`` FASYNC_MAGIC 0x4601 fasync_struct ``include/linux/fs.h``
SLIP_MAGIC 0x5302 slip ``drivers/net/slip.h`` SLIP_MAGIC 0x5302 slip ``drivers/net/slip.h``
MGSLPC_MAGIC 0x5402 mgslpc_info ``drivers/char/pcmcia/synclink_cs.c``
BAYCOM_MAGIC 0x19730510 baycom_state ``drivers/net/baycom_epp.c`` BAYCOM_MAGIC 0x19730510 baycom_state ``drivers/net/baycom_epp.c``
HDLCDRV_MAGIC 0x5ac6e778 hdlcdrv_state ``include/linux/hdlcdrv.h`` HDLCDRV_MAGIC 0x5ac6e778 hdlcdrv_state ``include/linux/hdlcdrv.h``
KV_MAGIC 0x5f4b565f kernel_vars_s ``arch/mips/include/asm/sn/klkernvars.h`` KV_MAGIC 0x5f4b565f kernel_vars_s ``arch/mips/include/asm/sn/klkernvars.h``
......
...@@ -222,7 +222,6 @@ Code Seq# Include File Comments ...@@ -222,7 +222,6 @@ Code Seq# Include File Comments
'b' 00-FF conflict! bit3 vme host bridge 'b' 00-FF conflict! bit3 vme host bridge
<mailto:natalia@nikhefk.nikhef.nl> <mailto:natalia@nikhefk.nikhef.nl>
'b' 00-0F linux/dma-buf.h conflict! 'b' 00-0F linux/dma-buf.h conflict!
'c' all linux/cm4000_cs.h conflict!
'c' 00-7F linux/comstats.h conflict! 'c' 00-7F linux/comstats.h conflict!
'c' 00-7F linux/coda.h conflict! 'c' 00-7F linux/coda.h conflict!
'c' 00-1F linux/chio.h conflict! 'c' 00-1F linux/chio.h conflict!
......
...@@ -964,6 +964,14 @@ Q: https://patchwork.kernel.org/project/linux-rdma/list/ ...@@ -964,6 +964,14 @@ Q: https://patchwork.kernel.org/project/linux-rdma/list/
F: drivers/infiniband/hw/efa/ F: drivers/infiniband/hw/efa/
F: include/uapi/rdma/efa-abi.h F: include/uapi/rdma/efa-abi.h
AMD CDX BUS DRIVER
M: Nipun Gupta <nipun.gupta@amd.com>
M: Nikhil Agarwal <nikhil.agarwal@amd.com>
S: Maintained
F: Documentation/devicetree/bindings/bus/xlnx,versal-net-cdx.yaml
F: drivers/cdx/*
F: include/linux/cdx/*
AMD CRYPTOGRAPHIC COPROCESSOR (CCP) DRIVER AMD CRYPTOGRAPHIC COPROCESSOR (CCP) DRIVER
M: Tom Lendacky <thomas.lendacky@amd.com> M: Tom Lendacky <thomas.lendacky@amd.com>
M: John Allen <john.allen@amd.com> M: John Allen <john.allen@amd.com>
...@@ -1431,11 +1439,6 @@ S: Supported ...@@ -1431,11 +1439,6 @@ S: Supported
F: drivers/clk/analogbits/* F: drivers/clk/analogbits/*
F: include/linux/clk/analogbits* F: include/linux/clk/analogbits*
ANDROID CONFIG FRAGMENTS
M: Rob Herring <robh@kernel.org>
S: Supported
F: kernel/configs/android*
ANDROID DRIVERS ANDROID DRIVERS
M: Greg Kroah-Hartman <gregkh@linuxfoundation.org> M: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
M: Arve Hjønnevåg <arve@android.com> M: Arve Hjønnevåg <arve@android.com>
...@@ -2095,7 +2098,6 @@ F: arch/arm/boot/dts/cx92755* ...@@ -2095,7 +2098,6 @@ F: arch/arm/boot/dts/cx92755*
N: digicolor N: digicolor
ARM/CORESIGHT FRAMEWORK AND DRIVERS ARM/CORESIGHT FRAMEWORK AND DRIVERS
M: Mathieu Poirier <mathieu.poirier@linaro.org>
M: Suzuki K Poulose <suzuki.poulose@arm.com> M: Suzuki K Poulose <suzuki.poulose@arm.com>
R: Mike Leach <mike.leach@linaro.org> R: Mike Leach <mike.leach@linaro.org>
R: Leo Yan <leo.yan@linaro.org> R: Leo Yan <leo.yan@linaro.org>
...@@ -10005,6 +10007,13 @@ F: Documentation/ABI/testing/sysfs-bus-iio-adc-envelope-detector ...@@ -10005,6 +10007,13 @@ F: Documentation/ABI/testing/sysfs-bus-iio-adc-envelope-detector
F: Documentation/devicetree/bindings/iio/adc/envelope-detector.yaml F: Documentation/devicetree/bindings/iio/adc/envelope-detector.yaml
F: drivers/iio/adc/envelope-detector.c F: drivers/iio/adc/envelope-detector.c
IIO LIGHT SENSOR GAIN-TIME-SCALE HELPERS
M: Matti Vaittinen <mazziesaccount@gmail.com>
L: linux-iio@vger.kernel.org
S: Maintained
F: drivers/iio/light/gain-time-scale-helper.c
F: drivers/iio/light/gain-time-scale-helper.h
IIO MULTIPLEXER IIO MULTIPLEXER
M: Peter Rosin <peda@axentia.se> M: Peter Rosin <peda@axentia.se>
L: linux-iio@vger.kernel.org L: linux-iio@vger.kernel.org
...@@ -10528,6 +10537,7 @@ F: drivers/watchdog/mei_wdt.c ...@@ -10528,6 +10537,7 @@ F: drivers/watchdog/mei_wdt.c
F: include/linux/mei_aux.h F: include/linux/mei_aux.h
F: include/linux/mei_cl_bus.h F: include/linux/mei_cl_bus.h
F: include/uapi/linux/mei.h F: include/uapi/linux/mei.h
F: include/uapi/linux/mei_uuid.h
F: include/uapi/linux/uuid.h F: include/uapi/linux/uuid.h
F: samples/mei/* F: samples/mei/*
...@@ -15411,18 +15421,6 @@ S: Maintained ...@@ -15411,18 +15421,6 @@ S: Maintained
F: Documentation/filesystems/omfs.rst F: Documentation/filesystems/omfs.rst
F: fs/omfs/ F: fs/omfs/
OMNIKEY CARDMAN 4000 DRIVER
M: Harald Welte <laforge@gnumonks.org>
S: Maintained
F: drivers/char/pcmcia/cm4000_cs.c
F: include/linux/cm4000_cs.h
F: include/uapi/linux/cm4000_cs.h
OMNIKEY CARDMAN 4040 DRIVER
M: Harald Welte <laforge@gnumonks.org>
S: Maintained
F: drivers/char/pcmcia/cm4040_cs.*
OMNIVISION OG01A1B SENSOR DRIVER OMNIVISION OG01A1B SENSOR DRIVER
M: Shawn Tu <shawnx.tu@intel.com> M: Shawn Tu <shawnx.tu@intel.com>
L: linux-media@vger.kernel.org L: linux-media@vger.kernel.org
...@@ -15640,6 +15638,12 @@ L: linux-hwmon@vger.kernel.org ...@@ -15640,6 +15638,12 @@ L: linux-hwmon@vger.kernel.org
S: Maintained S: Maintained
F: drivers/hwmon/oxp-sensors.c F: drivers/hwmon/oxp-sensors.c
ONIE TLV NVMEM LAYOUT DRIVER
M: Miquel Raynal <miquel.raynal@bootlin.com>
S: Maintained
F: Documentation/devicetree/bindings/nvmem/layouts/onie,tlv-layout.yaml
F: drivers/nvmem/layouts/onie-tlv.c
ONION OMEGA2+ BOARD ONION OMEGA2+ BOARD
M: Harvey Hunt <harveyhuntnexus@gmail.com> M: Harvey Hunt <harveyhuntnexus@gmail.com>
L: linux-mips@vger.kernel.org L: linux-mips@vger.kernel.org
...@@ -18203,6 +18207,12 @@ S: Maintained ...@@ -18203,6 +18207,12 @@ S: Maintained
F: Documentation/devicetree/bindings/iio/light/bh1750.yaml F: Documentation/devicetree/bindings/iio/light/bh1750.yaml
F: drivers/iio/light/bh1750.c F: drivers/iio/light/bh1750.c
ROHM BU27034 AMBIENT LIGHT SENSOR DRIVER
M: Matti Vaittinen <mazziesaccount@gmail.com>
L: linux-iio@vger.kernel.org
S: Supported
F: drivers/iio/light/rohm-bu27034.c
ROHM MULTIFUNCTION BD9571MWV-M PMIC DEVICE DRIVERS ROHM MULTIFUNCTION BD9571MWV-M PMIC DEVICE DRIVERS
M: Marek Vasut <marek.vasut+renesas@gmail.com> M: Marek Vasut <marek.vasut+renesas@gmail.com>
L: linux-kernel@vger.kernel.org L: linux-kernel@vger.kernel.org
...@@ -18727,11 +18737,6 @@ F: include/linux/wait.h ...@@ -18727,11 +18737,6 @@ F: include/linux/wait.h
F: include/uapi/linux/sched.h F: include/uapi/linux/sched.h
F: kernel/sched/ F: kernel/sched/
SCR24X CHIP CARD INTERFACE DRIVER
M: Lubomir Rintel <lkundrak@v3.sk>
S: Supported
F: drivers/char/pcmcia/scr24x_cs.c
SCSI RDMA PROTOCOL (SRP) INITIATOR SCSI RDMA PROTOCOL (SRP) INITIATOR
M: Bart Van Assche <bvanassche@acm.org> M: Bart Van Assche <bvanassche@acm.org>
L: linux-rdma@vger.kernel.org L: linux-rdma@vger.kernel.org
...@@ -19310,6 +19315,12 @@ F: drivers/irqchip/irq-sl28cpld.c ...@@ -19310,6 +19315,12 @@ F: drivers/irqchip/irq-sl28cpld.c
F: drivers/pwm/pwm-sl28cpld.c F: drivers/pwm/pwm-sl28cpld.c
F: drivers/watchdog/sl28cpld_wdt.c F: drivers/watchdog/sl28cpld_wdt.c
SL28 VPD NVMEM LAYOUT DRIVER
M: Michael Walle <michael@walle.cc>
S: Maintained
F: Documentation/devicetree/bindings/nvmem/layouts/kontron,sl28-vpd.yaml
F: drivers/nvmem/layouts/sl28vpd.c
SLAB ALLOCATOR SLAB ALLOCATOR
M: Christoph Lameter <cl@linux.com> M: Christoph Lameter <cl@linux.com>
M: Pekka Enberg <penberg@kernel.org> M: Pekka Enberg <penberg@kernel.org>
...@@ -22566,7 +22577,7 @@ S: Orphan ...@@ -22566,7 +22577,7 @@ S: Orphan
F: drivers/mmc/host/vub300.c F: drivers/mmc/host/vub300.c
W1 DALLAS'S 1-WIRE BUS W1 DALLAS'S 1-WIRE BUS
M: Evgeniy Polyakov <zbr@ioremap.net> M: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
S: Maintained S: Maintained
F: Documentation/devicetree/bindings/w1/ F: Documentation/devicetree/bindings/w1/
F: Documentation/w1/ F: Documentation/w1/
......
...@@ -614,8 +614,6 @@ CONFIG_HW_RANDOM=y ...@@ -614,8 +614,6 @@ CONFIG_HW_RANDOM=y
CONFIG_HW_RANDOM_VIRTIO=m CONFIG_HW_RANDOM_VIRTIO=m
CONFIG_NVRAM=y CONFIG_NVRAM=y
CONFIG_DTLK=m CONFIG_DTLK=m
CONFIG_CARDMAN_4000=m
CONFIG_CARDMAN_4040=m
CONFIG_IPWIRELESS=m CONFIG_IPWIRELESS=m
CONFIG_I2C_CHARDEV=m CONFIG_I2C_CHARDEV=m
CONFIG_I2C_HYDRA=m CONFIG_I2C_HYDRA=m
......
...@@ -241,4 +241,6 @@ source "drivers/peci/Kconfig" ...@@ -241,4 +241,6 @@ source "drivers/peci/Kconfig"
source "drivers/hte/Kconfig" source "drivers/hte/Kconfig"
source "drivers/cdx/Kconfig"
endmenu endmenu
...@@ -194,3 +194,4 @@ obj-$(CONFIG_MOST) += most/ ...@@ -194,3 +194,4 @@ obj-$(CONFIG_MOST) += most/
obj-$(CONFIG_PECI) += peci/ obj-$(CONFIG_PECI) += peci/
obj-$(CONFIG_HTE) += hte/ obj-$(CONFIG_HTE) += hte/
obj-$(CONFIG_DRM_ACCEL) += accel/ obj-$(CONFIG_DRM_ACCEL) += accel/
obj-$(CONFIG_CDX_BUS) += cdx/
...@@ -810,9 +810,10 @@ static bool acpi_of_modalias(struct acpi_device *adev, ...@@ -810,9 +810,10 @@ static bool acpi_of_modalias(struct acpi_device *adev,
* @modalias: Pointer to buffer that modalias value will be copied into * @modalias: Pointer to buffer that modalias value will be copied into
* @len: Length of modalias buffer * @len: Length of modalias buffer
* *
* This is a counterpart of of_modalias_node() for struct acpi_device objects. * This is a counterpart of of_alias_from_compatible() for struct acpi_device
* If there is a compatible string for @adev, it will be copied to @modalias * objects. If there is a compatible string for @adev, it will be copied to
* with the vendor prefix stripped; otherwise, @default_id will be used. * @modalias with the vendor prefix stripped; otherwise, @default_id will be
* used.
*/ */
void acpi_set_modalias(struct acpi_device *adev, const char *default_id, void acpi_set_modalias(struct acpi_device *adev, const char *default_id,
char *modalias, size_t len) char *modalias, size_t len)
......
...@@ -126,7 +126,7 @@ static int mhi_ep_process_cmd_ring(struct mhi_ep_ring *ring, struct mhi_ring_ele ...@@ -126,7 +126,7 @@ static int mhi_ep_process_cmd_ring(struct mhi_ep_ring *ring, struct mhi_ring_ele
/* Check if the channel is supported by the controller */ /* Check if the channel is supported by the controller */
if ((ch_id >= mhi_cntrl->max_chan) || !mhi_cntrl->mhi_chan[ch_id].name) { if ((ch_id >= mhi_cntrl->max_chan) || !mhi_cntrl->mhi_chan[ch_id].name) {
dev_err(dev, "Channel (%u) not supported!\n", ch_id); dev_dbg(dev, "Channel (%u) not supported!\n", ch_id);
return -ENODEV; return -ENODEV;
} }
...@@ -702,7 +702,7 @@ static void mhi_ep_cmd_ring_worker(struct work_struct *work) ...@@ -702,7 +702,7 @@ static void mhi_ep_cmd_ring_worker(struct work_struct *work)
el = &ring->ring_cache[ring->rd_offset]; el = &ring->ring_cache[ring->rd_offset];
ret = mhi_ep_process_cmd_ring(ring, el); ret = mhi_ep_process_cmd_ring(ring, el);
if (ret) if (ret && ret != -ENODEV)
dev_err(dev, "Error processing cmd ring element: %zu\n", ring->rd_offset); dev_err(dev, "Error processing cmd ring element: %zu\n", ring->rd_offset);
mhi_ep_ring_inc_index(ring); mhi_ep_ring_inc_index(ring);
......
...@@ -391,6 +391,7 @@ void mhi_fw_load_handler(struct mhi_controller *mhi_cntrl) ...@@ -391,6 +391,7 @@ void mhi_fw_load_handler(struct mhi_controller *mhi_cntrl)
{ {
const struct firmware *firmware = NULL; const struct firmware *firmware = NULL;
struct device *dev = &mhi_cntrl->mhi_dev->dev; struct device *dev = &mhi_cntrl->mhi_dev->dev;
enum mhi_pm_state new_state;
const char *fw_name; const char *fw_name;
void *buf; void *buf;
dma_addr_t dma_addr; dma_addr_t dma_addr;
...@@ -508,7 +509,10 @@ void mhi_fw_load_handler(struct mhi_controller *mhi_cntrl) ...@@ -508,7 +509,10 @@ void mhi_fw_load_handler(struct mhi_controller *mhi_cntrl)
} }
error_fw_load: error_fw_load:
mhi_cntrl->pm_state = MHI_PM_FW_DL_ERR; write_lock_irq(&mhi_cntrl->pm_lock);
new_state = mhi_tryset_pm_state(mhi_cntrl, MHI_PM_FW_DL_ERR);
write_unlock_irq(&mhi_cntrl->pm_lock);
if (new_state == MHI_PM_FW_DL_ERR)
wake_up_all(&mhi_cntrl->state_event); wake_up_all(&mhi_cntrl->state_event);
} }
...@@ -516,6 +520,7 @@ int mhi_download_amss_image(struct mhi_controller *mhi_cntrl) ...@@ -516,6 +520,7 @@ int mhi_download_amss_image(struct mhi_controller *mhi_cntrl)
{ {
struct image_info *image_info = mhi_cntrl->fbc_image; struct image_info *image_info = mhi_cntrl->fbc_image;
struct device *dev = &mhi_cntrl->mhi_dev->dev; struct device *dev = &mhi_cntrl->mhi_dev->dev;
enum mhi_pm_state new_state;
int ret; int ret;
if (!image_info) if (!image_info)
...@@ -526,7 +531,10 @@ int mhi_download_amss_image(struct mhi_controller *mhi_cntrl) ...@@ -526,7 +531,10 @@ int mhi_download_amss_image(struct mhi_controller *mhi_cntrl)
&image_info->mhi_buf[image_info->entries - 1]); &image_info->mhi_buf[image_info->entries - 1]);
if (ret) { if (ret) {
dev_err(dev, "MHI did not load AMSS, ret:%d\n", ret); dev_err(dev, "MHI did not load AMSS, ret:%d\n", ret);
mhi_cntrl->pm_state = MHI_PM_FW_DL_ERR; write_lock_irq(&mhi_cntrl->pm_lock);
new_state = mhi_tryset_pm_state(mhi_cntrl, MHI_PM_FW_DL_ERR);
write_unlock_irq(&mhi_cntrl->pm_lock);
if (new_state == MHI_PM_FW_DL_ERR)
wake_up_all(&mhi_cntrl->state_event); wake_up_all(&mhi_cntrl->state_event);
} }
......
...@@ -516,6 +516,12 @@ int mhi_init_mmio(struct mhi_controller *mhi_cntrl) ...@@ -516,6 +516,12 @@ int mhi_init_mmio(struct mhi_controller *mhi_cntrl)
return -EIO; return -EIO;
} }
if (val >= mhi_cntrl->reg_len - (8 * MHI_DEV_WAKE_DB)) {
dev_err(dev, "CHDB offset: 0x%x is out of range: 0x%zx\n",
val, mhi_cntrl->reg_len - (8 * MHI_DEV_WAKE_DB));
return -ERANGE;
}
/* Setup wake db */ /* Setup wake db */
mhi_cntrl->wake_db = base + val + (8 * MHI_DEV_WAKE_DB); mhi_cntrl->wake_db = base + val + (8 * MHI_DEV_WAKE_DB);
mhi_cntrl->wake_set = false; mhi_cntrl->wake_set = false;
...@@ -532,6 +538,12 @@ int mhi_init_mmio(struct mhi_controller *mhi_cntrl) ...@@ -532,6 +538,12 @@ int mhi_init_mmio(struct mhi_controller *mhi_cntrl)
return -EIO; return -EIO;
} }
if (val >= mhi_cntrl->reg_len - (8 * mhi_cntrl->total_ev_rings)) {
dev_err(dev, "ERDB offset: 0x%x is out of range: 0x%zx\n",
val, mhi_cntrl->reg_len - (8 * mhi_cntrl->total_ev_rings));
return -ERANGE;
}
/* Setup event db address for each ev_ring */ /* Setup event db address for each ev_ring */
mhi_event = mhi_cntrl->mhi_event; mhi_event = mhi_cntrl->mhi_event;
for (i = 0; i < mhi_cntrl->total_ev_rings; i++, val += 8, mhi_event++) { for (i = 0; i < mhi_cntrl->total_ev_rings; i++, val += 8, mhi_event++) {
...@@ -1100,7 +1112,7 @@ int mhi_prepare_for_power_up(struct mhi_controller *mhi_cntrl) ...@@ -1100,7 +1112,7 @@ int mhi_prepare_for_power_up(struct mhi_controller *mhi_cntrl)
if (bhi_off >= mhi_cntrl->reg_len) { if (bhi_off >= mhi_cntrl->reg_len) {
dev_err(dev, "BHI offset: 0x%x is out of range: 0x%zx\n", dev_err(dev, "BHI offset: 0x%x is out of range: 0x%zx\n",
bhi_off, mhi_cntrl->reg_len); bhi_off, mhi_cntrl->reg_len);
ret = -EINVAL; ret = -ERANGE;
goto error_reg_offset; goto error_reg_offset;
} }
mhi_cntrl->bhi = mhi_cntrl->regs + bhi_off; mhi_cntrl->bhi = mhi_cntrl->regs + bhi_off;
...@@ -1117,7 +1129,7 @@ int mhi_prepare_for_power_up(struct mhi_controller *mhi_cntrl) ...@@ -1117,7 +1129,7 @@ int mhi_prepare_for_power_up(struct mhi_controller *mhi_cntrl)
dev_err(dev, dev_err(dev,
"BHIe offset: 0x%x is out of range: 0x%zx\n", "BHIe offset: 0x%x is out of range: 0x%zx\n",
bhie_off, mhi_cntrl->reg_len); bhie_off, mhi_cntrl->reg_len);
ret = -EINVAL; ret = -ERANGE;
goto error_reg_offset; goto error_reg_offset;
} }
mhi_cntrl->bhie = mhi_cntrl->regs + bhie_off; mhi_cntrl->bhie = mhi_cntrl->regs + bhie_off;
......
...@@ -503,7 +503,7 @@ irqreturn_t mhi_intvec_threaded_handler(int irq_number, void *priv) ...@@ -503,7 +503,7 @@ irqreturn_t mhi_intvec_threaded_handler(int irq_number, void *priv)
} }
write_unlock_irq(&mhi_cntrl->pm_lock); write_unlock_irq(&mhi_cntrl->pm_lock);
if (pm_state != MHI_PM_SYS_ERR_DETECT || ee == mhi_cntrl->ee) if (pm_state != MHI_PM_SYS_ERR_DETECT)
goto exit_intvec; goto exit_intvec;
switch (ee) { switch (ee) {
...@@ -961,7 +961,9 @@ int mhi_process_ctrl_ev_ring(struct mhi_controller *mhi_cntrl, ...@@ -961,7 +961,9 @@ int mhi_process_ctrl_ev_ring(struct mhi_controller *mhi_cntrl,
} }
read_lock_bh(&mhi_cntrl->pm_lock); read_lock_bh(&mhi_cntrl->pm_lock);
if (likely(MHI_DB_ACCESS_VALID(mhi_cntrl)))
/* Ring EV DB only if there is any pending element to process */
if (likely(MHI_DB_ACCESS_VALID(mhi_cntrl)) && count)
mhi_ring_er_db(mhi_event); mhi_ring_er_db(mhi_event);
read_unlock_bh(&mhi_cntrl->pm_lock); read_unlock_bh(&mhi_cntrl->pm_lock);
...@@ -1031,7 +1033,9 @@ int mhi_process_data_event_ring(struct mhi_controller *mhi_cntrl, ...@@ -1031,7 +1033,9 @@ int mhi_process_data_event_ring(struct mhi_controller *mhi_cntrl,
count++; count++;
} }
read_lock_bh(&mhi_cntrl->pm_lock); read_lock_bh(&mhi_cntrl->pm_lock);
if (likely(MHI_DB_ACCESS_VALID(mhi_cntrl)))
/* Ring EV DB only if there is any pending element to process */
if (likely(MHI_DB_ACCESS_VALID(mhi_cntrl)) && count)
mhi_ring_er_db(mhi_event); mhi_ring_er_db(mhi_event);
read_unlock_bh(&mhi_cntrl->pm_lock); read_unlock_bh(&mhi_cntrl->pm_lock);
...@@ -1679,18 +1683,3 @@ void mhi_unprepare_from_transfer(struct mhi_device *mhi_dev) ...@@ -1679,18 +1683,3 @@ void mhi_unprepare_from_transfer(struct mhi_device *mhi_dev)
} }
} }
EXPORT_SYMBOL_GPL(mhi_unprepare_from_transfer); EXPORT_SYMBOL_GPL(mhi_unprepare_from_transfer);
int mhi_poll(struct mhi_device *mhi_dev, u32 budget)
{
struct mhi_controller *mhi_cntrl = mhi_dev->mhi_cntrl;
struct mhi_chan *mhi_chan = mhi_dev->dl_chan;
struct mhi_event *mhi_event = &mhi_cntrl->mhi_event[mhi_chan->er_index];
int ret;
spin_lock_bh(&mhi_event->lock);
ret = mhi_event->process_event(mhi_cntrl, mhi_event, budget);
spin_unlock_bh(&mhi_event->lock);
return ret;
}
EXPORT_SYMBOL_GPL(mhi_poll);
...@@ -8,7 +8,6 @@ ...@@ -8,7 +8,6 @@
* Copyright (C) 2020 Linaro Ltd <loic.poulain@linaro.org> * Copyright (C) 2020 Linaro Ltd <loic.poulain@linaro.org>
*/ */
#include <linux/aer.h>
#include <linux/delay.h> #include <linux/delay.h>
#include <linux/device.h> #include <linux/device.h>
#include <linux/mhi.h> #include <linux/mhi.h>
...@@ -344,8 +343,6 @@ static const struct mhi_channel_config mhi_foxconn_sdx55_channels[] = { ...@@ -344,8 +343,6 @@ static const struct mhi_channel_config mhi_foxconn_sdx55_channels[] = {
MHI_CHANNEL_CONFIG_DL(13, "MBIM", 32, 0), MHI_CHANNEL_CONFIG_DL(13, "MBIM", 32, 0),
MHI_CHANNEL_CONFIG_UL(32, "DUN", 32, 0), MHI_CHANNEL_CONFIG_UL(32, "DUN", 32, 0),
MHI_CHANNEL_CONFIG_DL(33, "DUN", 32, 0), MHI_CHANNEL_CONFIG_DL(33, "DUN", 32, 0),
MHI_CHANNEL_CONFIG_UL(92, "DUN2", 32, 1),
MHI_CHANNEL_CONFIG_DL(93, "DUN2", 32, 1),
MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0_MBIM", 128, 2), MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0_MBIM", 128, 2),
MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0_MBIM", 128, 3), MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0_MBIM", 128, 3),
}; };
...@@ -366,6 +363,15 @@ static const struct mhi_controller_config modem_foxconn_sdx55_config = { ...@@ -366,6 +363,15 @@ static const struct mhi_controller_config modem_foxconn_sdx55_config = {
.event_cfg = mhi_foxconn_sdx55_events, .event_cfg = mhi_foxconn_sdx55_events,
}; };
static const struct mhi_pci_dev_info mhi_foxconn_sdx24_info = {
.name = "foxconn-sdx24",
.config = &modem_foxconn_sdx55_config,
.bar_num = MHI_PCI_DEFAULT_BAR_NUM,
.dma_data_width = 32,
.mru_default = 32768,
.sideband_wake = false,
};
static const struct mhi_pci_dev_info mhi_foxconn_sdx55_info = { static const struct mhi_pci_dev_info mhi_foxconn_sdx55_info = {
.name = "foxconn-sdx55", .name = "foxconn-sdx55",
.fw = "qcom/sdx55m/sbl1.mbn", .fw = "qcom/sdx55m/sbl1.mbn",
...@@ -590,6 +596,15 @@ static const struct pci_device_id mhi_pci_id_table[] = { ...@@ -590,6 +596,15 @@ static const struct pci_device_id mhi_pci_id_table[] = {
/* T99W373 (sdx62) */ /* T99W373 (sdx62) */
{ PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0d9), { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0d9),
.driver_data = (kernel_ulong_t) &mhi_foxconn_sdx65_info }, .driver_data = (kernel_ulong_t) &mhi_foxconn_sdx65_info },
/* T99W510 (sdx24), variant 1 */
{ PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0f0),
.driver_data = (kernel_ulong_t) &mhi_foxconn_sdx24_info },
/* T99W510 (sdx24), variant 2 */
{ PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0f1),
.driver_data = (kernel_ulong_t) &mhi_foxconn_sdx24_info },
/* T99W510 (sdx24), variant 3 */
{ PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0f2),
.driver_data = (kernel_ulong_t) &mhi_foxconn_sdx24_info },
/* MV31-W (Cinterion) */ /* MV31-W (Cinterion) */
{ PCI_DEVICE(PCI_VENDOR_ID_THALES, 0x00b3), { PCI_DEVICE(PCI_VENDOR_ID_THALES, 0x00b3),
.driver_data = (kernel_ulong_t) &mhi_mv31_info }, .driver_data = (kernel_ulong_t) &mhi_mv31_info },
...@@ -903,11 +918,9 @@ static int mhi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) ...@@ -903,11 +918,9 @@ static int mhi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
mhi_pdev->pci_state = pci_store_saved_state(pdev); mhi_pdev->pci_state = pci_store_saved_state(pdev);
pci_load_saved_state(pdev, NULL); pci_load_saved_state(pdev, NULL);
pci_enable_pcie_error_reporting(pdev);
err = mhi_register_controller(mhi_cntrl, mhi_cntrl_config); err = mhi_register_controller(mhi_cntrl, mhi_cntrl_config);
if (err) if (err)
goto err_disable_reporting; return err;
/* MHI bus does not power up the controller by default */ /* MHI bus does not power up the controller by default */
err = mhi_prepare_for_power_up(mhi_cntrl); err = mhi_prepare_for_power_up(mhi_cntrl);
...@@ -941,8 +954,6 @@ static int mhi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) ...@@ -941,8 +954,6 @@ static int mhi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
mhi_unprepare_after_power_down(mhi_cntrl); mhi_unprepare_after_power_down(mhi_cntrl);
err_unregister: err_unregister:
mhi_unregister_controller(mhi_cntrl); mhi_unregister_controller(mhi_cntrl);
err_disable_reporting:
pci_disable_pcie_error_reporting(pdev);
return err; return err;
} }
...@@ -965,7 +976,6 @@ static void mhi_pci_remove(struct pci_dev *pdev) ...@@ -965,7 +976,6 @@ static void mhi_pci_remove(struct pci_dev *pdev)
pm_runtime_get_noresume(&pdev->dev); pm_runtime_get_noresume(&pdev->dev);
mhi_unregister_controller(mhi_cntrl); mhi_unregister_controller(mhi_cntrl);
pci_disable_pcie_error_reporting(pdev);
} }
static void mhi_pci_shutdown(struct pci_dev *pdev) static void mhi_pci_shutdown(struct pci_dev *pdev)
......
# SPDX-License-Identifier: GPL-2.0
#
# CDX bus configuration
#
# Copyright (C) 2022-2023, Advanced Micro Devices, Inc.
#
config CDX_BUS
bool "CDX Bus driver"
depends on OF && ARM64
help
Driver to enable Composable DMA Transfer(CDX) Bus. CDX bus
exposes Fabric devices which uses composable DMA IP to the
APU. CDX bus provides a mechanism for scanning and probing
of CDX devices. CDX devices are memory mapped on system bus
for embedded CPUs. CDX bus uses CDX controller and firmware
to scan these CDX devices.
source "drivers/cdx/controller/Kconfig"
# SPDX-License-Identifier: GPL-2.0
#
# Makefile for CDX
#
# Copyright (C) 2022-2023, Advanced Micro Devices, Inc.
#
obj-$(CONFIG_CDX_BUS) += cdx.o controller/
This diff is collapsed.
/* SPDX-License-Identifier: GPL-2.0
*
* Header file for the CDX Bus
*
* Copyright (C) 2022-2023, Advanced Micro Devices, Inc.
*/
#ifndef _CDX_H_
#define _CDX_H_
#include <linux/cdx/cdx_bus.h>
/**
* struct cdx_dev_params - CDX device parameters
* @cdx: CDX controller associated with the device
* @parent: Associated CDX controller
* @vendor: Vendor ID for CDX device
* @device: Device ID for CDX device
* @bus_num: Bus number for this CDX device
* @dev_num: Device number for this device
* @res: array of MMIO region entries
* @res_count: number of valid MMIO regions
* @req_id: Requestor ID associated with CDX device
*/
struct cdx_dev_params {
struct cdx_controller *cdx;
u16 vendor;
u16 device;
u8 bus_num;
u8 dev_num;
struct resource res[MAX_CDX_DEV_RESOURCES];
u8 res_count;
u32 req_id;
};
/**
* cdx_register_controller - Register a CDX controller and its ports
* on the CDX bus.
* @cdx: The CDX controller to register
*
* Return: -errno on failure, 0 on success.
*/
int cdx_register_controller(struct cdx_controller *cdx);
/**
* cdx_unregister_controller - Unregister a CDX controller
* @cdx: The CDX controller to unregister
*/
void cdx_unregister_controller(struct cdx_controller *cdx);
/**
* cdx_device_add - Add a CDX device. This function adds a CDX device
* on the CDX bus as per the device parameters provided
* by caller. It also creates and registers an associated
* Linux generic device.
* @dev_params: device parameters associated with the device to be created.
*
* Return: -errno on failure, 0 on success.
*/
int cdx_device_add(struct cdx_dev_params *dev_params);
#endif /* _CDX_H_ */
# SPDX-License-Identifier: GPL-2.0-only
#
# CDX controller configuration
#
# Copyright (C) 2022-2023, Advanced Micro Devices, Inc.
#
if CDX_BUS
config CDX_CONTROLLER
tristate "CDX bus controller"
select REMOTEPROC
select RPMSG
help
CDX controller drives the CDX bus. It interacts with
firmware to get the hardware devices and registers with
the CDX bus. Say Y to enable the CDX hardware driver.
If unsure, say N.
config MCDI_LOGGING
bool "MCDI Logging for the CDX controller"
depends on CDX_CONTROLLER
help
Enable MCDI Logging for
the CDX Controller for debug
purpose.
If unsure, say N.
endif
# SPDX-License-Identifier: GPL-2.0-only
#
# Makefile for CDX controller drivers
#
# Copyright (C) 2022-2023, Advanced Micro Devices, Inc.
#
obj-$(CONFIG_CDX_CONTROLLER) += cdx-controller.o
cdx-controller-objs := cdx_controller.o cdx_rpmsg.o mcdi.o mcdi_functions.o
/* SPDX-License-Identifier: GPL-2.0
*
* Copyright 2005-2006 Fen Systems Ltd.
* Copyright 2006-2013 Solarflare Communications Inc.
* Copyright (C) 2022-2023, Advanced Micro Devices, Inc.
*/
#ifndef CDX_BITFIELD_H
#define CDX_BITFIELD_H
#include <linux/bitfield.h>
/* Lowest bit numbers and widths */
#define CDX_DWORD_LBN 0
#define CDX_DWORD_WIDTH 32
/* Specified attribute (e.g. LBN) of the specified field */
#define CDX_VAL(field, attribute) field ## _ ## attribute
/* Low bit number of the specified field */
#define CDX_LOW_BIT(field) CDX_VAL(field, LBN)
/* Bit width of the specified field */
#define CDX_WIDTH(field) CDX_VAL(field, WIDTH)
/* High bit number of the specified field */
#define CDX_HIGH_BIT(field) (CDX_LOW_BIT(field) + CDX_WIDTH(field) - 1)
/* A doubleword (i.e. 4 byte) datatype - little-endian in HW */
struct cdx_dword {
__le32 cdx_u32;
};
/* Value expanders for printk */
#define CDX_DWORD_VAL(dword) \
((unsigned int)le32_to_cpu((dword).cdx_u32))
/*
* Extract bit field portion [low,high) from the 32-bit little-endian
* element which contains bits [min,max)
*/
#define CDX_DWORD_FIELD(dword, field) \
(FIELD_GET(GENMASK(CDX_HIGH_BIT(field), CDX_LOW_BIT(field)), \
le32_to_cpu((dword).cdx_u32)))
/*
* Creates the portion of the named bit field that lies within the
* range [min,max).
*/
#define CDX_INSERT_FIELD(field, value) \
(FIELD_PREP(GENMASK(CDX_HIGH_BIT(field), \
CDX_LOW_BIT(field)), value))
/*
* Creates the portion of the named bit fields that lie within the
* range [min,max).
*/
#define CDX_INSERT_FIELDS(field1, value1, \
field2, value2, \
field3, value3, \
field4, value4, \
field5, value5, \
field6, value6, \
field7, value7) \
(CDX_INSERT_FIELD(field1, (value1)) | \
CDX_INSERT_FIELD(field2, (value2)) | \
CDX_INSERT_FIELD(field3, (value3)) | \
CDX_INSERT_FIELD(field4, (value4)) | \
CDX_INSERT_FIELD(field5, (value5)) | \
CDX_INSERT_FIELD(field6, (value6)) | \
CDX_INSERT_FIELD(field7, (value7)))
#define CDX_POPULATE_DWORD(dword, ...) \
(dword).cdx_u32 = cpu_to_le32(CDX_INSERT_FIELDS(__VA_ARGS__))
/* Populate a dword field with various numbers of arguments */
#define CDX_POPULATE_DWORD_7 CDX_POPULATE_DWORD
#define CDX_POPULATE_DWORD_6(dword, ...) \
CDX_POPULATE_DWORD_7(dword, CDX_DWORD, 0, __VA_ARGS__)
#define CDX_POPULATE_DWORD_5(dword, ...) \
CDX_POPULATE_DWORD_6(dword, CDX_DWORD, 0, __VA_ARGS__)
#define CDX_POPULATE_DWORD_4(dword, ...) \
CDX_POPULATE_DWORD_5(dword, CDX_DWORD, 0, __VA_ARGS__)
#define CDX_POPULATE_DWORD_3(dword, ...) \
CDX_POPULATE_DWORD_4(dword, CDX_DWORD, 0, __VA_ARGS__)
#define CDX_POPULATE_DWORD_2(dword, ...) \
CDX_POPULATE_DWORD_3(dword, CDX_DWORD, 0, __VA_ARGS__)
#define CDX_POPULATE_DWORD_1(dword, ...) \
CDX_POPULATE_DWORD_2(dword, CDX_DWORD, 0, __VA_ARGS__)
#define CDX_SET_DWORD(dword) \
CDX_POPULATE_DWORD_1(dword, CDX_DWORD, 0xffffffff)
#endif /* CDX_BITFIELD_H */
// SPDX-License-Identifier: GPL-2.0
/*
* CDX host controller driver for AMD versal-net platform.
*
* Copyright (C) 2022-2023, Advanced Micro Devices, Inc.
*/
#include <linux/of_platform.h>
#include <linux/slab.h>
#include <linux/cdx/cdx_bus.h>
#include "cdx_controller.h"
#include "../cdx.h"
#include "mcdi_functions.h"
#include "mcdi.h"
static unsigned int cdx_mcdi_rpc_timeout(struct cdx_mcdi *cdx, unsigned int cmd)
{
return MCDI_RPC_TIMEOUT;
}
static void cdx_mcdi_request(struct cdx_mcdi *cdx,
const struct cdx_dword *hdr, size_t hdr_len,
const struct cdx_dword *sdu, size_t sdu_len)
{
if (cdx_rpmsg_send(cdx, hdr, hdr_len, sdu, sdu_len))
dev_err(&cdx->rpdev->dev, "Failed to send rpmsg data\n");
}
static const struct cdx_mcdi_ops mcdi_ops = {
.mcdi_rpc_timeout = cdx_mcdi_rpc_timeout,
.mcdi_request = cdx_mcdi_request,
};
void cdx_rpmsg_post_probe(struct cdx_controller *cdx)
{
/* Register CDX controller with CDX bus driver */
if (cdx_register_controller(cdx))
dev_err(cdx->dev, "Failed to register CDX controller\n");
}
void cdx_rpmsg_pre_remove(struct cdx_controller *cdx)
{
cdx_unregister_controller(cdx);
cdx_mcdi_wait_for_quiescence(cdx->priv, MCDI_RPC_TIMEOUT);
}
static int cdx_configure_device(struct cdx_controller *cdx,
u8 bus_num, u8 dev_num,
struct cdx_device_config *dev_config)
{
int ret = 0;
switch (dev_config->type) {
case CDX_DEV_RESET_CONF:
ret = cdx_mcdi_reset_device(cdx->priv, bus_num, dev_num);
break;
default:
ret = -EINVAL;
}
return ret;
}
static int cdx_scan_devices(struct cdx_controller *cdx)
{
struct cdx_mcdi *cdx_mcdi = cdx->priv;
u8 bus_num, dev_num, num_cdx_bus;
int ret;
/* MCDI FW Read: Fetch the number of CDX buses on this controller */
ret = cdx_mcdi_get_num_buses(cdx_mcdi);
if (ret < 0) {
dev_err(cdx->dev,
"Get number of CDX buses failed: %d\n", ret);
return ret;
}
num_cdx_bus = (u8)ret;
for (bus_num = 0; bus_num < num_cdx_bus; bus_num++) {
u8 num_cdx_dev;
/* MCDI FW Read: Fetch the number of devices present */
ret = cdx_mcdi_get_num_devs(cdx_mcdi, bus_num);
if (ret < 0) {
dev_err(cdx->dev,
"Get devices on CDX bus %d failed: %d\n", bus_num, ret);
continue;
}
num_cdx_dev = (u8)ret;
for (dev_num = 0; dev_num < num_cdx_dev; dev_num++) {
struct cdx_dev_params dev_params;
/* MCDI FW: Get the device config */
ret = cdx_mcdi_get_dev_config(cdx_mcdi, bus_num,
dev_num, &dev_params);
if (ret) {
dev_err(cdx->dev,
"CDX device config get failed for %d(bus):%d(dev), %d\n",
bus_num, dev_num, ret);
continue;
}
dev_params.cdx = cdx;
/* Add the device to the cdx bus */
ret = cdx_device_add(&dev_params);
if (ret) {
dev_err(cdx->dev, "registering cdx dev: %d failed: %d\n",
dev_num, ret);
continue;
}
dev_dbg(cdx->dev, "CDX dev: %d on cdx bus: %d created\n",
dev_num, bus_num);
}
}
return 0;
}
static struct cdx_ops cdx_ops = {
.scan = cdx_scan_devices,
.dev_configure = cdx_configure_device,
};
static int xlnx_cdx_probe(struct platform_device *pdev)
{
struct cdx_controller *cdx;
struct cdx_mcdi *cdx_mcdi;
int ret;
cdx_mcdi = kzalloc(sizeof(*cdx_mcdi), GFP_KERNEL);
if (!cdx_mcdi)
return -ENOMEM;
/* Store the MCDI ops */
cdx_mcdi->mcdi_ops = &mcdi_ops;
/* MCDI FW: Initialize the FW path */
ret = cdx_mcdi_init(cdx_mcdi);
if (ret) {
dev_err_probe(&pdev->dev, ret, "MCDI Initialization failed\n");
goto mcdi_init_fail;
}
cdx = kzalloc(sizeof(*cdx), GFP_KERNEL);
if (!cdx) {
ret = -ENOMEM;
goto cdx_alloc_fail;
}
platform_set_drvdata(pdev, cdx);
cdx->dev = &pdev->dev;
cdx->priv = cdx_mcdi;
cdx->ops = &cdx_ops;
ret = cdx_setup_rpmsg(pdev);
if (ret) {
if (ret != -EPROBE_DEFER)
dev_err(&pdev->dev, "Failed to register CDX RPMsg transport\n");
goto cdx_rpmsg_fail;
}
dev_info(&pdev->dev, "Successfully registered CDX controller with RPMsg as transport\n");
return 0;
cdx_rpmsg_fail:
kfree(cdx);
cdx_alloc_fail:
cdx_mcdi_finish(cdx_mcdi);
mcdi_init_fail:
kfree(cdx_mcdi);
return ret;
}
static int xlnx_cdx_remove(struct platform_device *pdev)
{
struct cdx_controller *cdx = platform_get_drvdata(pdev);
struct cdx_mcdi *cdx_mcdi = cdx->priv;
cdx_destroy_rpmsg(pdev);
kfree(cdx);
cdx_mcdi_finish(cdx_mcdi);
kfree(cdx_mcdi);
return 0;
}
static const struct of_device_id cdx_match_table[] = {
{.compatible = "xlnx,versal-net-cdx",},
{ },
};
MODULE_DEVICE_TABLE(of, cdx_match_table);
static struct platform_driver cdx_pdriver = {
.driver = {
.name = "cdx-controller",
.pm = NULL,
.of_match_table = cdx_match_table,
},
.probe = xlnx_cdx_probe,
.remove = xlnx_cdx_remove,
};
static int __init cdx_controller_init(void)
{
int ret;
ret = platform_driver_register(&cdx_pdriver);
if (ret)
pr_err("platform_driver_register() failed: %d\n", ret);
return ret;
}
static void __exit cdx_controller_exit(void)
{
platform_driver_unregister(&cdx_pdriver);
}
module_init(cdx_controller_init);
module_exit(cdx_controller_exit);
MODULE_AUTHOR("AMD Inc.");
MODULE_DESCRIPTION("CDX controller for AMD devices");
MODULE_LICENSE("GPL");
/* SPDX-License-Identifier: GPL-2.0
*
* Header file for the CDX Controller
*
* Copyright (C) 2022-2023, Advanced Micro Devices, Inc.
*/
#ifndef _CDX_CONTROLLER_H_
#define _CDX_CONTROLLER_H_
#include <linux/cdx/cdx_bus.h>
#include "mcdi_functions.h"
void cdx_rpmsg_post_probe(struct cdx_controller *cdx);
void cdx_rpmsg_pre_remove(struct cdx_controller *cdx);
int cdx_rpmsg_send(struct cdx_mcdi *cdx_mcdi,
const struct cdx_dword *hdr, size_t hdr_len,
const struct cdx_dword *sdu, size_t sdu_len);
void cdx_rpmsg_read_resp(struct cdx_mcdi *cdx_mcdi,
struct cdx_dword *outbuf, size_t offset,
size_t outlen);
int cdx_setup_rpmsg(struct platform_device *pdev);
void cdx_destroy_rpmsg(struct platform_device *pdev);
#endif /* _CDX_CONT_PRIV_H_ */
// SPDX-License-Identifier: GPL-2.0
/*
* Platform driver for CDX bus.
*
* Copyright (C) 2022-2023, Advanced Micro Devices, Inc.
*/
#include <linux/rpmsg.h>
#include <linux/remoteproc.h>
#include <linux/of_platform.h>
#include <linux/cdx/cdx_bus.h>
#include <linux/module.h>
#include "../cdx.h"
#include "cdx_controller.h"
#include "mcdi_functions.h"
#include "mcdi.h"
static struct rpmsg_device_id cdx_rpmsg_id_table[] = {
{ .name = "mcdi_ipc" },
{ },
};
MODULE_DEVICE_TABLE(rpmsg, cdx_rpmsg_id_table);
int cdx_rpmsg_send(struct cdx_mcdi *cdx_mcdi,
const struct cdx_dword *hdr, size_t hdr_len,
const struct cdx_dword *sdu, size_t sdu_len)
{
unsigned char *send_buf;
int ret;
send_buf = kzalloc(hdr_len + sdu_len, GFP_KERNEL);
if (!send_buf)
return -ENOMEM;
memcpy(send_buf, hdr, hdr_len);
memcpy(send_buf + hdr_len, sdu, sdu_len);
ret = rpmsg_send(cdx_mcdi->ept, send_buf, hdr_len + sdu_len);
kfree(send_buf);
return ret;
}
static int cdx_attach_to_rproc(struct platform_device *pdev)
{
struct device_node *r5_core_node;
struct cdx_controller *cdx_c;
struct cdx_mcdi *cdx_mcdi;
struct device *dev;
struct rproc *rp;
int ret;
dev = &pdev->dev;
cdx_c = platform_get_drvdata(pdev);
cdx_mcdi = cdx_c->priv;
r5_core_node = of_parse_phandle(dev->of_node, "xlnx,rproc", 0);
if (!r5_core_node) {
dev_err(&pdev->dev, "xlnx,rproc: invalid phandle\n");
return -EINVAL;
}
rp = rproc_get_by_phandle(r5_core_node->phandle);
if (!rp) {
ret = -EPROBE_DEFER;
goto pdev_err;
}
/* Attach to remote processor */
ret = rproc_boot(rp);
if (ret) {
dev_err(&pdev->dev, "Failed to attach to remote processor\n");
rproc_put(rp);
goto pdev_err;
}
cdx_mcdi->r5_rproc = rp;
pdev_err:
of_node_put(r5_core_node);
return ret;
}
static void cdx_detach_to_r5(struct platform_device *pdev)
{
struct cdx_controller *cdx_c;
struct cdx_mcdi *cdx_mcdi;
cdx_c = platform_get_drvdata(pdev);
cdx_mcdi = cdx_c->priv;
rproc_detach(cdx_mcdi->r5_rproc);
rproc_put(cdx_mcdi->r5_rproc);
}
static int cdx_rpmsg_cb(struct rpmsg_device *rpdev, void *data,
int len, void *priv, u32 src)
{
struct cdx_controller *cdx_c = dev_get_drvdata(&rpdev->dev);
struct cdx_mcdi *cdx_mcdi = cdx_c->priv;
if (len > MCDI_BUF_LEN)
return -EINVAL;
cdx_mcdi_process_cmd(cdx_mcdi, (struct cdx_dword *)data, len);
return 0;
}
static void cdx_rpmsg_post_probe_work(struct work_struct *work)
{
struct cdx_controller *cdx_c;
struct cdx_mcdi *cdx_mcdi;
cdx_mcdi = container_of(work, struct cdx_mcdi, work);
cdx_c = dev_get_drvdata(&cdx_mcdi->rpdev->dev);
cdx_rpmsg_post_probe(cdx_c);
}
static int cdx_rpmsg_probe(struct rpmsg_device *rpdev)
{
struct rpmsg_channel_info chinfo = {0};
struct cdx_controller *cdx_c;
struct cdx_mcdi *cdx_mcdi;
cdx_c = (struct cdx_controller *)cdx_rpmsg_id_table[0].driver_data;
cdx_mcdi = cdx_c->priv;
chinfo.src = RPMSG_ADDR_ANY;
chinfo.dst = rpdev->dst;
strscpy(chinfo.name, cdx_rpmsg_id_table[0].name,
strlen(cdx_rpmsg_id_table[0].name));
cdx_mcdi->ept = rpmsg_create_ept(rpdev, cdx_rpmsg_cb, NULL, chinfo);
if (!cdx_mcdi->ept) {
dev_err_probe(&rpdev->dev, -ENXIO,
"Failed to create ept for channel %s\n",
chinfo.name);
return -EINVAL;
}
cdx_mcdi->rpdev = rpdev;
dev_set_drvdata(&rpdev->dev, cdx_c);
schedule_work(&cdx_mcdi->work);
return 0;
}
static void cdx_rpmsg_remove(struct rpmsg_device *rpdev)
{
struct cdx_controller *cdx_c = dev_get_drvdata(&rpdev->dev);
struct cdx_mcdi *cdx_mcdi = cdx_c->priv;
flush_work(&cdx_mcdi->work);
cdx_rpmsg_pre_remove(cdx_c);
rpmsg_destroy_ept(cdx_mcdi->ept);
dev_set_drvdata(&rpdev->dev, NULL);
}
static struct rpmsg_driver cdx_rpmsg_driver = {
.drv.name = KBUILD_MODNAME,
.id_table = cdx_rpmsg_id_table,
.probe = cdx_rpmsg_probe,
.remove = cdx_rpmsg_remove,
.callback = cdx_rpmsg_cb,
};
int cdx_setup_rpmsg(struct platform_device *pdev)
{
struct cdx_controller *cdx_c;
struct cdx_mcdi *cdx_mcdi;
int ret;
/* Attach to remote processor */
ret = cdx_attach_to_rproc(pdev);
if (ret)
return ret;
cdx_c = platform_get_drvdata(pdev);
cdx_mcdi = cdx_c->priv;
/* Register RPMsg driver */
cdx_rpmsg_id_table[0].driver_data = (kernel_ulong_t)cdx_c;
INIT_WORK(&cdx_mcdi->work, cdx_rpmsg_post_probe_work);
ret = register_rpmsg_driver(&cdx_rpmsg_driver);
if (ret) {
dev_err(&pdev->dev,
"Failed to register cdx RPMsg driver: %d\n", ret);
cdx_detach_to_r5(pdev);
}
return ret;
}
void cdx_destroy_rpmsg(struct platform_device *pdev)
{
unregister_rpmsg_driver(&cdx_rpmsg_driver);
cdx_detach_to_r5(pdev);
}
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/* SPDX-License-Identifier: GPL-2.0
*
* Copyright 2008-2013 Solarflare Communications Inc.
* Copyright (C) 2022-2023, Advanced Micro Devices, Inc.
*/
#ifndef CDX_MCDI_H
#define CDX_MCDI_H
#include <linux/mutex.h>
#include <linux/kref.h>
#include <linux/rpmsg.h>
#include "bitfield.h"
#include "mc_cdx_pcol.h"
#ifdef DEBUG
#define CDX_WARN_ON_ONCE_PARANOID(x) WARN_ON_ONCE(x)
#define CDX_WARN_ON_PARANOID(x) WARN_ON(x)
#else
#define CDX_WARN_ON_ONCE_PARANOID(x) do {} while (0)
#define CDX_WARN_ON_PARANOID(x) do {} while (0)
#endif
/**
* enum cdx_mcdi_mode - MCDI transaction mode
* @MCDI_MODE_EVENTS: wait for an mcdi response callback.
* @MCDI_MODE_FAIL: we think MCDI is dead, so fail-fast all calls
*/
enum cdx_mcdi_mode {
MCDI_MODE_EVENTS,
MCDI_MODE_FAIL,
};
#define MCDI_RPC_TIMEOUT (10 * HZ)
#define MCDI_RPC_LONG_TIMEOU (60 * HZ)
#define MCDI_RPC_POST_RST_TIME (10 * HZ)
#define MCDI_BUF_LEN (8 + MCDI_CTL_SDU_LEN_MAX)
/**
* enum cdx_mcdi_cmd_state - State for an individual MCDI command
* @MCDI_STATE_QUEUED: Command not started and is waiting to run.
* @MCDI_STATE_RETRY: Command was submitted and MC rejected with no resources,
* as MC have too many outstanding commands. Command will be retried once
* another command returns.
* @MCDI_STATE_RUNNING: Command was accepted and is running.
* @MCDI_STATE_RUNNING_CANCELLED: Command is running but the issuer cancelled
* the command.
* @MCDI_STATE_FINISHED: Processing of this command has completed.
*/
enum cdx_mcdi_cmd_state {
MCDI_STATE_QUEUED,
MCDI_STATE_RETRY,
MCDI_STATE_RUNNING,
MCDI_STATE_RUNNING_CANCELLED,
MCDI_STATE_FINISHED,
};
/**
* struct cdx_mcdi - CDX MCDI Firmware interface, to interact
* with CDX controller.
* @mcdi: MCDI interface
* @mcdi_ops: MCDI operations
* @r5_rproc : R5 Remoteproc device handle
* @rpdev: RPMsg device
* @ept: RPMsg endpoint
* @work: Post probe work
*/
struct cdx_mcdi {
/* MCDI interface */
struct cdx_mcdi_data *mcdi;
const struct cdx_mcdi_ops *mcdi_ops;
struct rproc *r5_rproc;
struct rpmsg_device *rpdev;
struct rpmsg_endpoint *ept;
struct work_struct work;
};
struct cdx_mcdi_ops {
void (*mcdi_request)(struct cdx_mcdi *cdx,
const struct cdx_dword *hdr, size_t hdr_len,
const struct cdx_dword *sdu, size_t sdu_len);
unsigned int (*mcdi_rpc_timeout)(struct cdx_mcdi *cdx, unsigned int cmd);
};
typedef void cdx_mcdi_async_completer(struct cdx_mcdi *cdx,
unsigned long cookie, int rc,
struct cdx_dword *outbuf,
size_t outlen_actual);
/**
* struct cdx_mcdi_cmd - An outstanding MCDI command
* @ref: Reference count. There will be one reference if the command is
* in the mcdi_iface cmd_list, another if it's on a cleanup list,
* and a third if it's queued in the work queue.
* @list: The data for this entry in mcdi->cmd_list
* @cleanup_list: The data for this entry in a cleanup list
* @work: The work item for this command, queued in mcdi->workqueue
* @mcdi: The mcdi_iface for this command
* @state: The state of this command
* @inlen: inbuf length
* @inbuf: Input buffer
* @quiet: Whether to silence errors
* @reboot_seen: Whether a reboot has been seen during this command,
* to prevent duplicates
* @seq: Sequence number
* @started: Jiffies this command was started at
* @cookie: Context for completion function
* @completer: Completion function
* @handle: Command handle
* @cmd: Command number
* @rc: Return code
* @outlen: Length of output buffer
* @outbuf: Output buffer
*/
struct cdx_mcdi_cmd {
struct kref ref;
struct list_head list;
struct list_head cleanup_list;
struct work_struct work;
struct cdx_mcdi_iface *mcdi;
enum cdx_mcdi_cmd_state state;
size_t inlen;
const struct cdx_dword *inbuf;
bool quiet;
bool reboot_seen;
u8 seq;
unsigned long started;
unsigned long cookie;
cdx_mcdi_async_completer *completer;
unsigned int handle;
unsigned int cmd;
int rc;
size_t outlen;
struct cdx_dword *outbuf;
/* followed by inbuf data if necessary */
};
/**
* struct cdx_mcdi_iface - MCDI protocol context
* @cdx: The associated NIC
* @iface_lock: Serialise access to this structure
* @outstanding_cleanups: Count of cleanups
* @cmd_list: List of outstanding and running commands
* @workqueue: Workqueue used for delayed processing
* @cmd_complete_wq: Waitqueue for command completion
* @db_held_by: Command the MC doorbell is in use by
* @seq_held_by: Command each sequence number is in use by
* @prev_handle: The last used command handle
* @mode: Poll for mcdi completion, or wait for an mcdi_event
* @prev_seq: The last used sequence number
* @new_epoch: Indicates start of day or start of MC reboot recovery
* @logging_buffer: Buffer that may be used to build MCDI tracing messages
* @logging_enabled: Whether to trace MCDI
*/
struct cdx_mcdi_iface {
struct cdx_mcdi *cdx;
/* Serialise access */
struct mutex iface_lock;
unsigned int outstanding_cleanups;
struct list_head cmd_list;
struct workqueue_struct *workqueue;
wait_queue_head_t cmd_complete_wq;
struct cdx_mcdi_cmd *db_held_by;
struct cdx_mcdi_cmd *seq_held_by[16];
unsigned int prev_handle;
enum cdx_mcdi_mode mode;
u8 prev_seq;
bool new_epoch;
#ifdef CONFIG_MCDI_LOGGING
bool logging_enabled;
char *logging_buffer;
#endif
};
/**
* struct cdx_mcdi_data - extra state for NICs that implement MCDI
* @iface: Interface/protocol state
* @fn_flags: Flags for this function, as returned by %MC_CMD_DRV_ATTACH.
*/
struct cdx_mcdi_data {
struct cdx_mcdi_iface iface;
u32 fn_flags;
};
static inline struct cdx_mcdi_iface *cdx_mcdi_if(struct cdx_mcdi *cdx)
{
return cdx->mcdi ? &cdx->mcdi->iface : NULL;
}
int cdx_mcdi_init(struct cdx_mcdi *cdx);
void cdx_mcdi_finish(struct cdx_mcdi *cdx);
void cdx_mcdi_process_cmd(struct cdx_mcdi *cdx, struct cdx_dword *outbuf, int len);
int cdx_mcdi_rpc(struct cdx_mcdi *cdx, unsigned int cmd,
const struct cdx_dword *inbuf, size_t inlen,
struct cdx_dword *outbuf, size_t outlen, size_t *outlen_actual);
int cdx_mcdi_rpc_async(struct cdx_mcdi *cdx, unsigned int cmd,
const struct cdx_dword *inbuf, size_t inlen,
cdx_mcdi_async_completer *complete,
unsigned long cookie);
int cdx_mcdi_wait_for_quiescence(struct cdx_mcdi *cdx,
unsigned int timeout_jiffies);
/*
* We expect that 16- and 32-bit fields in MCDI requests and responses
* are appropriately aligned, but 64-bit fields are only
* 32-bit-aligned.
*/
#define MCDI_DECLARE_BUF(_name, _len) struct cdx_dword _name[DIV_ROUND_UP(_len, 4)] = {{0}}
#define _MCDI_PTR(_buf, _offset) \
((u8 *)(_buf) + (_offset))
#define MCDI_PTR(_buf, _field) \
_MCDI_PTR(_buf, MC_CMD_ ## _field ## _OFST)
#define _MCDI_CHECK_ALIGN(_ofst, _align) \
((void)BUILD_BUG_ON_ZERO((_ofst) & ((_align) - 1)), \
(_ofst))
#define _MCDI_DWORD(_buf, _field) \
((_buf) + (_MCDI_CHECK_ALIGN(MC_CMD_ ## _field ## _OFST, 4) >> 2))
#define MCDI_BYTE(_buf, _field) \
((void)BUILD_BUG_ON_ZERO(MC_CMD_ ## _field ## _LEN != 1), \
*MCDI_PTR(_buf, _field))
#define MCDI_WORD(_buf, _field) \
((void)BUILD_BUG_ON_ZERO(MC_CMD_ ## _field ## _LEN != 2), \
le16_to_cpu(*(__force const __le16 *)MCDI_PTR(_buf, _field)))
#define MCDI_SET_DWORD(_buf, _field, _value) \
CDX_POPULATE_DWORD_1(*_MCDI_DWORD(_buf, _field), CDX_DWORD, _value)
#define MCDI_DWORD(_buf, _field) \
CDX_DWORD_FIELD(*_MCDI_DWORD(_buf, _field), CDX_DWORD)
#define MCDI_POPULATE_DWORD_1(_buf, _field, _name1, _value1) \
CDX_POPULATE_DWORD_1(*_MCDI_DWORD(_buf, _field), \
MC_CMD_ ## _name1, _value1)
#define MCDI_SET_QWORD(_buf, _field, _value) \
do { \
CDX_POPULATE_DWORD_1(_MCDI_DWORD(_buf, _field)[0], \
CDX_DWORD, (u32)(_value)); \
CDX_POPULATE_DWORD_1(_MCDI_DWORD(_buf, _field)[1], \
CDX_DWORD, (u64)(_value) >> 32); \
} while (0)
#define MCDI_QWORD(_buf, _field) \
(CDX_DWORD_FIELD(_MCDI_DWORD(_buf, _field)[0], CDX_DWORD) | \
(u64)CDX_DWORD_FIELD(_MCDI_DWORD(_buf, _field)[1], CDX_DWORD) << 32)
#endif /* CDX_MCDI_H */
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2022-2023, Advanced Micro Devices, Inc.
*/
#include <linux/module.h>
#include "mcdi.h"
#include "mcdi_functions.h"
int cdx_mcdi_get_num_buses(struct cdx_mcdi *cdx)
{
MCDI_DECLARE_BUF(outbuf, MC_CMD_CDX_BUS_ENUM_BUSES_OUT_LEN);
size_t outlen;
int ret;
ret = cdx_mcdi_rpc(cdx, MC_CMD_CDX_BUS_ENUM_BUSES, NULL, 0,
outbuf, sizeof(outbuf), &outlen);
if (ret)
return ret;
if (outlen != MC_CMD_CDX_BUS_ENUM_BUSES_OUT_LEN)
return -EIO;
return MCDI_DWORD(outbuf, CDX_BUS_ENUM_BUSES_OUT_BUS_COUNT);
}
int cdx_mcdi_get_num_devs(struct cdx_mcdi *cdx, int bus_num)
{
MCDI_DECLARE_BUF(outbuf, MC_CMD_CDX_BUS_ENUM_DEVICES_OUT_LEN);
MCDI_DECLARE_BUF(inbuf, MC_CMD_CDX_BUS_ENUM_DEVICES_IN_LEN);
size_t outlen;
int ret;
MCDI_SET_DWORD(inbuf, CDX_BUS_ENUM_DEVICES_IN_BUS, bus_num);
ret = cdx_mcdi_rpc(cdx, MC_CMD_CDX_BUS_ENUM_DEVICES, inbuf, sizeof(inbuf),
outbuf, sizeof(outbuf), &outlen);
if (ret)
return ret;
if (outlen != MC_CMD_CDX_BUS_ENUM_DEVICES_OUT_LEN)
return -EIO;
return MCDI_DWORD(outbuf, CDX_BUS_ENUM_DEVICES_OUT_DEVICE_COUNT);
}
int cdx_mcdi_get_dev_config(struct cdx_mcdi *cdx,
u8 bus_num, u8 dev_num,
struct cdx_dev_params *dev_params)
{
MCDI_DECLARE_BUF(outbuf, MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_LEN);
MCDI_DECLARE_BUF(inbuf, MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_IN_LEN);
struct resource *res = &dev_params->res[0];
size_t outlen;
u32 req_id;
int ret;
MCDI_SET_DWORD(inbuf, CDX_BUS_GET_DEVICE_CONFIG_IN_BUS, bus_num);
MCDI_SET_DWORD(inbuf, CDX_BUS_GET_DEVICE_CONFIG_IN_DEVICE, dev_num);
ret = cdx_mcdi_rpc(cdx, MC_CMD_CDX_BUS_GET_DEVICE_CONFIG, inbuf, sizeof(inbuf),
outbuf, sizeof(outbuf), &outlen);
if (ret)
return ret;
if (outlen != MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_LEN)
return -EIO;
dev_params->bus_num = bus_num;
dev_params->dev_num = dev_num;
req_id = MCDI_DWORD(outbuf, CDX_BUS_GET_DEVICE_CONFIG_OUT_REQUESTER_ID);
dev_params->req_id = req_id;
dev_params->res_count = 0;
if (MCDI_QWORD(outbuf, CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION0_SIZE) != 0) {
res[dev_params->res_count].start =
MCDI_QWORD(outbuf, CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION0_BASE);
res[dev_params->res_count].end =
MCDI_QWORD(outbuf, CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION0_BASE) +
MCDI_QWORD(outbuf,
CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION0_SIZE) - 1;
res[dev_params->res_count].flags = IORESOURCE_MEM;
dev_params->res_count++;
}
if (MCDI_QWORD(outbuf, CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION1_SIZE) != 0) {
res[dev_params->res_count].start =
MCDI_QWORD(outbuf, CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION1_BASE);
res[dev_params->res_count].end =
MCDI_QWORD(outbuf, CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION1_BASE) +
MCDI_QWORD(outbuf,
CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION1_SIZE) - 1;
res[dev_params->res_count].flags = IORESOURCE_MEM;
dev_params->res_count++;
}
if (MCDI_QWORD(outbuf, CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION2_SIZE) != 0) {
res[dev_params->res_count].start =
MCDI_QWORD(outbuf, CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION2_BASE);
res[dev_params->res_count].end =
MCDI_QWORD(outbuf, CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION2_BASE) +
MCDI_QWORD(outbuf,
CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION2_SIZE) - 1;
res[dev_params->res_count].flags = IORESOURCE_MEM;
dev_params->res_count++;
}
if (MCDI_QWORD(outbuf, CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION3_SIZE) != 0) {
res[dev_params->res_count].start =
MCDI_QWORD(outbuf, CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION3_BASE);
res[dev_params->res_count].end =
MCDI_QWORD(outbuf, CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION3_BASE) +
MCDI_QWORD(outbuf,
CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION3_SIZE) - 1;
res[dev_params->res_count].flags = IORESOURCE_MEM;
dev_params->res_count++;
}
dev_params->vendor = MCDI_WORD(outbuf, CDX_BUS_GET_DEVICE_CONFIG_OUT_VENDOR_ID);
dev_params->device = MCDI_WORD(outbuf, CDX_BUS_GET_DEVICE_CONFIG_OUT_DEVICE_ID);
return 0;
}
int cdx_mcdi_reset_device(struct cdx_mcdi *cdx, u8 bus_num, u8 dev_num)
{
MCDI_DECLARE_BUF(inbuf, MC_CMD_CDX_DEVICE_RESET_IN_LEN);
int ret;
MCDI_SET_DWORD(inbuf, CDX_DEVICE_RESET_IN_BUS, bus_num);
MCDI_SET_DWORD(inbuf, CDX_DEVICE_RESET_IN_DEVICE, dev_num);
ret = cdx_mcdi_rpc(cdx, MC_CMD_CDX_DEVICE_RESET, inbuf, sizeof(inbuf),
NULL, 0, NULL);
return ret;
}
/* SPDX-License-Identifier: GPL-2.0
*
* Header file for MCDI FW interaction for CDX bus.
*
* Copyright (C) 2022-2023, Advanced Micro Devices, Inc.
*/
#ifndef CDX_MCDI_FUNCTIONS_H
#define CDX_MCDI_FUNCTIONS_H
#include "mcdi.h"
#include "../cdx.h"
/**
* cdx_mcdi_get_num_buses - Get the total number of buses on
* the controller.
* @cdx: pointer to MCDI interface.
*
* Return: total number of buses available on the controller,
* <0 on failure
*/
int cdx_mcdi_get_num_buses(struct cdx_mcdi *cdx);
/**
* cdx_mcdi_get_num_devs - Get the total number of devices on
* a particular bus of the controller.
* @cdx: pointer to MCDI interface.
* @bus_num: Bus number.
*
* Return: total number of devices available on the bus, <0 on failure
*/
int cdx_mcdi_get_num_devs(struct cdx_mcdi *cdx, int bus_num);
/**
* cdx_mcdi_get_dev_config - Get configuration for a particular
* bus_num:dev_num
* @cdx: pointer to MCDI interface.
* @bus_num: Bus number.
* @dev_num: Device number.
* @dev_params: Pointer to cdx_dev_params, this is populated by this
* device with the configuration corresponding to the provided
* bus_num:dev_num.
*
* Return: 0 total number of devices available on the bus, <0 on failure
*/
int cdx_mcdi_get_dev_config(struct cdx_mcdi *cdx,
u8 bus_num, u8 dev_num,
struct cdx_dev_params *dev_params);
/**
* cdx_mcdi_reset_device - Reset cdx device represented by bus_num:dev_num
* @cdx: pointer to MCDI interface.
* @bus_num: Bus number.
* @dev_num: Device number.
*
* Return: 0 on success, <0 on failure
*/
int cdx_mcdi_reset_device(struct cdx_mcdi *cdx,
u8 bus_num, u8 dev_num);
#endif /* CDX_MCDI_FUNCTIONS_H */
...@@ -247,8 +247,6 @@ config SONYPI ...@@ -247,8 +247,6 @@ config SONYPI
To compile this driver as a module, choose M here: the To compile this driver as a module, choose M here: the
module will be called sonypi. module will be called sonypi.
source "drivers/char/pcmcia/Kconfig"
config MWAVE config MWAVE
tristate "ACP Modem (Mwave) support" tristate "ACP Modem (Mwave) support"
depends on X86 && TTY depends on X86 && TTY
......
...@@ -35,7 +35,6 @@ obj-$(CONFIG_TELCLOCK) += tlclk.o ...@@ -35,7 +35,6 @@ obj-$(CONFIG_TELCLOCK) += tlclk.o
obj-$(CONFIG_MWAVE) += mwave/ obj-$(CONFIG_MWAVE) += mwave/
obj-y += agp/ obj-y += agp/
obj-$(CONFIG_PCMCIA) += pcmcia/
obj-$(CONFIG_HANGCHECK_TIMER) += hangcheck-timer.o obj-$(CONFIG_HANGCHECK_TIMER) += hangcheck-timer.o
obj-$(CONFIG_TCG_TPM) += tpm/ obj-$(CONFIG_TCG_TPM) += tpm/
......
# SPDX-License-Identifier: GPL-2.0-only
#
# PCMCIA character device configuration
#
menu "PCMCIA character devices"
depends on PCMCIA!=n
config SYNCLINK_CS
tristate "SyncLink PC Card support"
depends on PCMCIA && TTY
help
Enable support for the SyncLink PC Card serial adapter, running
asynchronous and HDLC communications up to 512Kbps. The port is
selectable for RS-232, V.35, RS-449, RS-530, and X.21
This driver may be built as a module ( = code which can be
inserted in and removed from the running kernel whenever you want).
The module will be called synclink_cs. If you want to do that, say M
here.
config CARDMAN_4000
tristate "Omnikey Cardman 4000 support"
depends on PCMCIA
select BITREVERSE
help
Enable support for the Omnikey Cardman 4000 PCMCIA Smartcard
reader.
This kernel driver requires additional userspace support, either
by the vendor-provided PC/SC ifd_handler (http://www.omnikey.com/),
or via the cm4000 backend of OpenCT (http://www.opensc-project.org/opensc).
config CARDMAN_4040
tristate "Omnikey CardMan 4040 support"
depends on PCMCIA
help
Enable support for the Omnikey CardMan 4040 PCMCIA Smartcard
reader.
This card is basically a USB CCID device connected to a FIFO
in I/O space. To use the kernel driver, you will need either the
PC/SC ifdhandler provided from the Omnikey homepage
(http://www.omnikey.com/), or a current development version of OpenCT
(http://www.opensc-project.org/opensc).
config SCR24X
tristate "SCR24x Chip Card Interface support"
depends on PCMCIA
help
Enable support for the SCR24x PCMCIA Chip Card Interface.
To compile this driver as a module, choose M here.
The module will be called scr24x_cs..
If unsure say N.
config IPWIRELESS
tristate "IPWireless 3G UMTS PCMCIA card support"
depends on PCMCIA && NETDEVICES && TTY
select PPP
help
This is a driver for 3G UMTS PCMCIA card from IPWireless company. In
some countries (for example Czech Republic, T-Mobile ISP) this card
is shipped for service called UMTS 4G.
endmenu
# SPDX-License-Identifier: GPL-2.0-only
#
# drivers/char/pcmcia/Makefile
#
# Makefile for the Linux PCMCIA char device drivers.
#
obj-$(CONFIG_SYNCLINK_CS) += synclink_cs.o
obj-$(CONFIG_CARDMAN_4000) += cm4000_cs.o
obj-$(CONFIG_CARDMAN_4040) += cm4040_cs.o
obj-$(CONFIG_SCR24X) += scr24x_cs.o
This diff is collapsed.
This diff is collapsed.
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _CM4040_H_
#define _CM4040_H_
#define CM_MAX_DEV 4
#define DEVICE_NAME "cmx"
#define MODULE_NAME "cm4040_cs"
#define REG_OFFSET_BULK_OUT 0
#define REG_OFFSET_BULK_IN 0
#define REG_OFFSET_BUFFER_STATUS 1
#define REG_OFFSET_SYNC_CONTROL 2
#define BSR_BULK_IN_FULL 0x02
#define BSR_BULK_OUT_FULL 0x01
#define SCR_HOST_TO_READER_START 0x80
#define SCR_ABORT 0x40
#define SCR_EN_NOTIFY 0x20
#define SCR_ACK_NOTIFY 0x10
#define SCR_READER_TO_HOST_DONE 0x08
#define SCR_HOST_TO_READER_DONE 0x04
#define SCR_PULSE_INTERRUPT 0x02
#define SCR_POWER_DOWN 0x01
#define CMD_PC_TO_RDR_ICCPOWERON 0x62
#define CMD_PC_TO_RDR_GETSLOTSTATUS 0x65
#define CMD_PC_TO_RDR_ICCPOWEROFF 0x63
#define CMD_PC_TO_RDR_SECURE 0x69
#define CMD_PC_TO_RDR_GETPARAMETERS 0x6C
#define CMD_PC_TO_RDR_RESETPARAMETERS 0x6D
#define CMD_PC_TO_RDR_SETPARAMETERS 0x61
#define CMD_PC_TO_RDR_XFRBLOCK 0x6F
#define CMD_PC_TO_RDR_ESCAPE 0x6B
#define CMD_PC_TO_RDR_ICCCLOCK 0x6E
#define CMD_PC_TO_RDR_TEST_SECURE 0x74
#define CMD_PC_TO_RDR_OK_SECURE 0x89
#define CMD_RDR_TO_PC_SLOTSTATUS 0x81
#define CMD_RDR_TO_PC_DATABLOCK 0x80
#define CMD_RDR_TO_PC_PARAMETERS 0x82
#define CMD_RDR_TO_PC_ESCAPE 0x83
#define CMD_RDR_TO_PC_OK_SECURE 0x89
#endif /* _CM4040_H_ */
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...@@ -304,7 +304,7 @@ static struct attribute *dmi_sysfs_sel_attrs[] = { ...@@ -304,7 +304,7 @@ static struct attribute *dmi_sysfs_sel_attrs[] = {
}; };
ATTRIBUTE_GROUPS(dmi_sysfs_sel); ATTRIBUTE_GROUPS(dmi_sysfs_sel);
static struct kobj_type dmi_system_event_log_ktype = { static const struct kobj_type dmi_system_event_log_ktype = {
.release = dmi_entry_free, .release = dmi_entry_free,
.sysfs_ops = &dmi_sysfs_specialize_attr_ops, .sysfs_ops = &dmi_sysfs_specialize_attr_ops,
.default_groups = dmi_sysfs_sel_groups, .default_groups = dmi_sysfs_sel_groups,
...@@ -563,7 +563,7 @@ static void dmi_sysfs_entry_release(struct kobject *kobj) ...@@ -563,7 +563,7 @@ static void dmi_sysfs_entry_release(struct kobject *kobj)
kfree(entry); kfree(entry);
} }
static struct kobj_type dmi_sysfs_entry_ktype = { static const struct kobj_type dmi_sysfs_entry_ktype = {
.release = dmi_sysfs_entry_release, .release = dmi_sysfs_entry_release,
.sysfs_ops = &dmi_sysfs_attr_ops, .sysfs_ops = &dmi_sysfs_attr_ops,
.default_groups = dmi_sysfs_entry_groups, .default_groups = dmi_sysfs_entry_groups,
......
...@@ -608,7 +608,7 @@ static void edd_release(struct kobject * kobj) ...@@ -608,7 +608,7 @@ static void edd_release(struct kobject * kobj)
kfree(dev); kfree(dev);
} }
static struct kobj_type edd_ktype = { static const struct kobj_type edd_ktype = {
.release = edd_release, .release = edd_release,
.sysfs_ops = &edd_attr_ops, .sysfs_ops = &edd_attr_ops,
}; };
......
...@@ -1133,8 +1133,8 @@ static int stratix10_svc_drv_probe(struct platform_device *pdev) ...@@ -1133,8 +1133,8 @@ static int stratix10_svc_drv_probe(struct platform_device *pdev)
return ret; return ret;
genpool = svc_create_memory_pool(pdev, sh_memory); genpool = svc_create_memory_pool(pdev, sh_memory);
if (!genpool) if (IS_ERR(genpool))
return -ENOMEM; return PTR_ERR(genpool);
/* allocate service controller and supporting channel */ /* allocate service controller and supporting channel */
controller = devm_kzalloc(dev, sizeof(*controller), GFP_KERNEL); controller = devm_kzalloc(dev, sizeof(*controller), GFP_KERNEL);
......
...@@ -971,6 +971,39 @@ int zynqmp_pm_fpga_get_status(u32 *value) ...@@ -971,6 +971,39 @@ int zynqmp_pm_fpga_get_status(u32 *value)
} }
EXPORT_SYMBOL_GPL(zynqmp_pm_fpga_get_status); EXPORT_SYMBOL_GPL(zynqmp_pm_fpga_get_status);
/**
* zynqmp_pm_fpga_get_config_status - Get the FPGA configuration status.
* @value: Buffer to store FPGA configuration status.
*
* This function provides access to the pmufw to get the FPGA configuration
* status
*
* Return: 0 on success, a negative value on error
*/
int zynqmp_pm_fpga_get_config_status(u32 *value)
{
u32 ret_payload[PAYLOAD_ARG_CNT];
u32 buf, lower_addr, upper_addr;
int ret;
if (!value)
return -EINVAL;
lower_addr = lower_32_bits((u64)&buf);
upper_addr = upper_32_bits((u64)&buf);
ret = zynqmp_pm_invoke_fn(PM_FPGA_READ,
XILINX_ZYNQMP_PM_FPGA_CONFIG_STAT_OFFSET,
lower_addr, upper_addr,
XILINX_ZYNQMP_PM_FPGA_READ_CONFIG_REG,
ret_payload);
*value = ret_payload[1];
return ret;
}
EXPORT_SYMBOL_GPL(zynqmp_pm_fpga_get_config_status);
/** /**
* zynqmp_pm_pinctrl_request - Request Pin from firmware * zynqmp_pm_pinctrl_request - Request Pin from firmware
* @pin: Pin number to request * @pin: Pin number to request
......
...@@ -115,7 +115,7 @@ static int fpga_bridge_dev_match(struct device *dev, const void *data) ...@@ -115,7 +115,7 @@ static int fpga_bridge_dev_match(struct device *dev, const void *data)
/** /**
* fpga_bridge_get - get an exclusive reference to an fpga bridge * fpga_bridge_get - get an exclusive reference to an fpga bridge
* @dev: parent device that fpga bridge was registered with * @dev: parent device that fpga bridge was registered with
* @info: fpga manager info * @info: fpga image specific information
* *
* Given a device, get an exclusive reference to an fpga bridge. * Given a device, get an exclusive reference to an fpga bridge.
* *
......
...@@ -77,6 +77,26 @@ static enum fpga_mgr_states zynqmp_fpga_ops_state(struct fpga_manager *mgr) ...@@ -77,6 +77,26 @@ static enum fpga_mgr_states zynqmp_fpga_ops_state(struct fpga_manager *mgr)
return FPGA_MGR_STATE_UNKNOWN; return FPGA_MGR_STATE_UNKNOWN;
} }
static ssize_t status_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
u32 status;
int ret;
ret = zynqmp_pm_fpga_get_config_status(&status);
if (ret)
return ret;
return sysfs_emit(buf, "0x%x\n", status);
}
static DEVICE_ATTR_RO(status);
static struct attribute *zynqmp_fpga_attrs[] = {
&dev_attr_status.attr,
NULL,
};
ATTRIBUTE_GROUPS(zynqmp_fpga);
static const struct fpga_manager_ops zynqmp_fpga_ops = { static const struct fpga_manager_ops zynqmp_fpga_ops = {
.state = zynqmp_fpga_ops_state, .state = zynqmp_fpga_ops_state,
.write_init = zynqmp_fpga_ops_write_init, .write_init = zynqmp_fpga_ops_write_init,
...@@ -113,6 +133,7 @@ static struct platform_driver zynqmp_fpga_driver = { ...@@ -113,6 +133,7 @@ static struct platform_driver zynqmp_fpga_driver = {
.driver = { .driver = {
.name = "zynqmp_fpga_manager", .name = "zynqmp_fpga_manager",
.of_match_table = of_match_ptr(zynqmp_fpga_of_match), .of_match_table = of_match_ptr(zynqmp_fpga_of_match),
.dev_groups = zynqmp_fpga_groups,
}, },
}; };
......
...@@ -160,7 +160,7 @@ of_mipi_dsi_device_add(struct mipi_dsi_host *host, struct device_node *node) ...@@ -160,7 +160,7 @@ of_mipi_dsi_device_add(struct mipi_dsi_host *host, struct device_node *node)
int ret; int ret;
u32 reg; u32 reg;
if (of_modalias_node(node, info.type, sizeof(info.type)) < 0) { if (of_alias_from_compatible(node, info.type, sizeof(info.type)) < 0) {
drm_err(host, "modalias failure on %pOF\n", node); drm_err(host, "modalias failure on %pOF\n", node);
return ERR_PTR(-EINVAL); return ERR_PTR(-EINVAL);
} }
......
...@@ -207,7 +207,7 @@ static void hsi_add_client_from_dt(struct hsi_port *port, ...@@ -207,7 +207,7 @@ static void hsi_add_client_from_dt(struct hsi_port *port,
if (!cl) if (!cl)
return; return;
err = of_modalias_node(client, name, sizeof(name)); err = of_alias_from_compatible(client, name, sizeof(name));
if (err) if (err)
goto err; goto err;
......
...@@ -901,6 +901,7 @@ int __init etm_perf_init(void) ...@@ -901,6 +901,7 @@ int __init etm_perf_init(void)
etm_pmu.addr_filters_sync = etm_addr_filters_sync; etm_pmu.addr_filters_sync = etm_addr_filters_sync;
etm_pmu.addr_filters_validate = etm_addr_filters_validate; etm_pmu.addr_filters_validate = etm_addr_filters_validate;
etm_pmu.nr_addr_filters = ETM_ADDR_CMP_MAX; etm_pmu.nr_addr_filters = ETM_ADDR_CMP_MAX;
etm_pmu.module = THIS_MODULE;
ret = perf_pmu_register(&etm_pmu, CORESIGHT_ETM_PMU_NAME, -1); ret = perf_pmu_register(&etm_pmu, CORESIGHT_ETM_PMU_NAME, -1);
if (ret == 0) if (ret == 0)
......
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