Commit cf21f328 authored by Laurent Pinchart's avatar Laurent Pinchart Committed by Mauro Carvalho Chehab

media: nxp: Add i.MX8 ISI driver

The Image Sensing Interface (ISI) combines image processing pipelines
with DMA engines to process and capture frames originating from a
variety of sources. The inputs to the ISI go through Pixel Link
interfaces, and their number and nature is SoC-dependent. They cover
both capture interfaces (MIPI CSI-2 RX, HDMI RX) and memory inputs.
Signed-off-by: default avatarChristian Hemp <c.hemp@phytec.de>
Signed-off-by: default avatarDong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: default avatarGuoniu Zhou <guoniu.zhou@nxp.com>
Signed-off-by: default avatarJacopo Mondi <jacopo@jmondi.org>
Signed-off-by: default avatarLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: default avatarStefan Riedmueller <s.riedmueller@phytec.de>
Tested-by: Adam Ford <aford173@gmail.com> #imx8mn-beacon
Signed-off-by: default avatarMauro Carvalho Chehab <mchehab@kernel.org>
parent b28e2418
......@@ -14931,6 +14931,13 @@ F: Documentation/devicetree/bindings/clock/imx*
F: drivers/clk/imx/
F: include/dt-bindings/clock/imx*
NXP i.MX 8M ISI DRIVER
M: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
L: linux-media@vger.kernel.org
S: Maintained
F: Documentation/devicetree/bindings/media/nxp,imx8-isi.yaml
F: drivers/media/platform/nxp/imx8-isi/
NXP i.MX 8MQ DCSS DRIVER
M: Laurentiu Palcu <laurentiu.palcu@oss.nxp.com>
R: Lucas Stach <l.stach@pengutronix.de>
......
......@@ -28,6 +28,8 @@ config VIDEO_IMX_MIPI_CSIS
Video4Linux2 sub-device driver for the MIPI CSI-2 CSIS receiver
v3.3/v3.6.3 found on some i.MX7 and i.MX8 SoCs.
source "drivers/media/platform/nxp/imx8-isi/Kconfig"
# mem2mem drivers
config VIDEO_IMX_PXP
......
......@@ -2,6 +2,7 @@
obj-y += dw100/
obj-y += imx-jpeg/
obj-y += imx8-isi/
obj-$(CONFIG_VIDEO_IMX7_CSI) += imx7-media-csi.o
obj-$(CONFIG_VIDEO_IMX_MIPI_CSIS) += imx-mipi-csis.o
......
# SPDX-License-Identifier: GPL-2.0-only
config VIDEO_IMX8_ISI
tristate "i.MX8 Image Sensor Interface (ISI) driver"
depends on ARCH_MXC || COMPILE_TEST
depends on HAS_DMA && PM
depends on VIDEO_DEV
select MEDIA_CONTROLLER
select V4L2_FWNODE
select V4L2_MEM2MEM_DEV if VIDEO_IMX8_ISI_M2M
select VIDEO_V4L2_SUBDEV_API
select VIDEOBUF2_DMA_CONTIG
help
V4L2 driver for the Image Sensor Interface (ISI) found in various
i.MX8 SoCs.
config VIDEO_IMX8_ISI_M2M
bool "i.MX8 Image Sensor Interface (ISI) memory-to-memory support"
depends on VIDEO_IMX8_ISI
help
Select 'yes' here to enable support for memory-to-memory processing
in the ISI driver.
# SPDX-License-Identifier: GPL-2.0-only
imx8-isi-y := imx8-isi-core.o imx8-isi-crossbar.o imx8-isi-hw.o \
imx8-isi-pipe.o imx8-isi-video.o
imx8-isi-$(CONFIG_DEBUG_FS) += imx8-isi-debug.o
imx8-isi-$(CONFIG_VIDEO_IMX8_ISI_M2M) += imx8-isi-m2m.o
obj-$(CONFIG_VIDEO_IMX8_ISI) += imx8-isi.o
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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2019-2020 NXP
*/
#include <linux/debugfs.h>
#include <linux/device.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/pm_runtime.h>
#include <linux/seq_file.h>
#include <linux/types.h>
#include "imx8-isi-core.h"
#include "imx8-isi-regs.h"
static inline u32 mxc_isi_read(struct mxc_isi_pipe *pipe, u32 reg)
{
return readl(pipe->regs + reg);
}
static int mxc_isi_debug_dump_regs_show(struct seq_file *m, void *p)
{
#define MXC_ISI_DEBUG_REG(name) { name, #name }
static const struct {
u32 offset;
const char * const name;
} registers[] = {
MXC_ISI_DEBUG_REG(CHNL_CTRL),
MXC_ISI_DEBUG_REG(CHNL_IMG_CTRL),
MXC_ISI_DEBUG_REG(CHNL_OUT_BUF_CTRL),
MXC_ISI_DEBUG_REG(CHNL_IMG_CFG),
MXC_ISI_DEBUG_REG(CHNL_IER),
MXC_ISI_DEBUG_REG(CHNL_STS),
MXC_ISI_DEBUG_REG(CHNL_SCALE_FACTOR),
MXC_ISI_DEBUG_REG(CHNL_SCALE_OFFSET),
MXC_ISI_DEBUG_REG(CHNL_CROP_ULC),
MXC_ISI_DEBUG_REG(CHNL_CROP_LRC),
MXC_ISI_DEBUG_REG(CHNL_CSC_COEFF0),
MXC_ISI_DEBUG_REG(CHNL_CSC_COEFF1),
MXC_ISI_DEBUG_REG(CHNL_CSC_COEFF2),
MXC_ISI_DEBUG_REG(CHNL_CSC_COEFF3),
MXC_ISI_DEBUG_REG(CHNL_CSC_COEFF4),
MXC_ISI_DEBUG_REG(CHNL_CSC_COEFF5),
MXC_ISI_DEBUG_REG(CHNL_ROI_0_ALPHA),
MXC_ISI_DEBUG_REG(CHNL_ROI_0_ULC),
MXC_ISI_DEBUG_REG(CHNL_ROI_0_LRC),
MXC_ISI_DEBUG_REG(CHNL_ROI_1_ALPHA),
MXC_ISI_DEBUG_REG(CHNL_ROI_1_ULC),
MXC_ISI_DEBUG_REG(CHNL_ROI_1_LRC),
MXC_ISI_DEBUG_REG(CHNL_ROI_2_ALPHA),
MXC_ISI_DEBUG_REG(CHNL_ROI_2_ULC),
MXC_ISI_DEBUG_REG(CHNL_ROI_2_LRC),
MXC_ISI_DEBUG_REG(CHNL_ROI_3_ALPHA),
MXC_ISI_DEBUG_REG(CHNL_ROI_3_ULC),
MXC_ISI_DEBUG_REG(CHNL_ROI_3_LRC),
MXC_ISI_DEBUG_REG(CHNL_OUT_BUF1_ADDR_Y),
MXC_ISI_DEBUG_REG(CHNL_OUT_BUF1_ADDR_U),
MXC_ISI_DEBUG_REG(CHNL_OUT_BUF1_ADDR_V),
MXC_ISI_DEBUG_REG(CHNL_OUT_BUF_PITCH),
MXC_ISI_DEBUG_REG(CHNL_IN_BUF_ADDR),
MXC_ISI_DEBUG_REG(CHNL_IN_BUF_PITCH),
MXC_ISI_DEBUG_REG(CHNL_MEM_RD_CTRL),
MXC_ISI_DEBUG_REG(CHNL_OUT_BUF2_ADDR_Y),
MXC_ISI_DEBUG_REG(CHNL_OUT_BUF2_ADDR_U),
MXC_ISI_DEBUG_REG(CHNL_OUT_BUF2_ADDR_V),
MXC_ISI_DEBUG_REG(CHNL_SCL_IMG_CFG),
MXC_ISI_DEBUG_REG(CHNL_FLOW_CTRL),
};
struct mxc_isi_pipe *pipe = m->private;
unsigned int i;
if (!pm_runtime_get_if_in_use(pipe->isi->dev))
return 0;
seq_printf(m, "--- ISI pipe %u registers ---\n", pipe->id);
for (i = 0; i < ARRAY_SIZE(registers); ++i)
seq_printf(m, "%20s[0x%02x]: 0x%08x\n",
registers[i].name, registers[i].offset,
mxc_isi_read(pipe, registers[i].offset));
pm_runtime_put(pipe->isi->dev);
return 0;
}
DEFINE_SHOW_ATTRIBUTE(mxc_isi_debug_dump_regs);
void mxc_isi_debug_init(struct mxc_isi_dev *isi)
{
unsigned int i;
isi->debugfs_root = debugfs_create_dir(dev_name(isi->dev), NULL);
for (i = 0; i < isi->pdata->num_channels; ++i) {
struct mxc_isi_pipe *pipe = &isi->pipes[i];
char name[8];
sprintf(name, "pipe%u", pipe->id);
debugfs_create_file(name, 0444, isi->debugfs_root, pipe,
&mxc_isi_debug_dump_regs_fops);
}
}
void mxc_isi_debug_cleanup(struct mxc_isi_dev *isi)
{
debugfs_remove_recursive(isi->debugfs_root);
}
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