drm/amd/display: separate dc_debug into dc_debug_options and dc_debug data

[why]
confusing as to which part of debug is informational, and which part causes behavioral change
Signed-off-by: Jun Lei <Jun.Lei@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c

@@ -676,7 +676,7 @@ static void hack_force_pipe_split(struct dcn_bw_internal_vars *v,
 }
 
 static void hack_bounding_box(struct dcn_bw_internal_vars *v,
-		struct dc_debug *dbg,
+		struct dc_debug_options *dbg,
 		struct dc_state *context)
 {
 	if (dbg->pipe_split_policy == MPC_SPLIT_AVOID)

drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c

@@ -1029,7 +1029,7 @@ enum link_training_result dc_link_dp_perform_link_training(
 			lt_settings.lane_settings[0].PRE_EMPHASIS);
 
 	if (status != LINK_TRAINING_SUCCESS)
-		link->ctx->dc->debug.debug_data.ltFailCount++;
+		link->ctx->dc->debug_data.ltFailCount++;
 
 	return status;
 }

drivers/gpu/drm/amd/display/dc/dc.h

@@ -207,7 +207,7 @@ struct dc_clocks {
 	int phyclk_khz;
 };
 
-struct dc_debug {
+struct dc_debug_options {
 	enum visual_confirm visual_confirm;
 	bool sanity_checks;
 	bool max_disp_clk;
@@ -259,13 +259,15 @@ struct dc_debug {
 	bool scl_reset_length10;
 	bool hdmi20_disable;
 	bool skip_detection_link_training;
+};
 
-	struct {
-		uint32_t ltFailCount;
-		uint32_t i2cErrorCount;
-		uint32_t auxErrorCount;
-	} debug_data;
+struct dc_debug_data {
+	uint32_t ltFailCount;
+	uint32_t i2cErrorCount;
+	uint32_t auxErrorCount;
 };
+
+
 struct dc_state;
 struct resource_pool;
 struct dce_hwseq;
@@ -274,8 +276,7 @@ struct dc {
 	struct dc_caps caps;
 	struct dc_cap_funcs cap_funcs;
 	struct dc_config config;
-	struct dc_debug debug;
-
+	struct dc_debug_options debug;
 	struct dc_context *ctx;
 
 	uint8_t link_count;
@@ -311,6 +312,8 @@ struct dc {
 
 	/* FBC compressor */
 	struct compressor *fbc_compressor;
+
+	struct dc_debug_data debug_data;
 };
 
 enum frame_buffer_mode {

drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c

@@ -337,7 +337,7 @@ static int dce112_set_clock(
 
 static void dce_clock_read_integrated_info(struct dce_dccg *clk_dce)
 {
-	struct dc_debug *debug = &clk_dce->base.ctx->dc->debug;
+	struct dc_debug_options *debug = &clk_dce->base.ctx->dc->debug;
 	struct dc_bios *bp = clk_dce->base.ctx->dc_bios;
 	struct integrated_info info = { { { 0 } } };
 	struct dc_firmware_info fw_info = { { 0 } };
@@ -824,7 +824,7 @@ struct dccg *dce120_dccg_create(struct dc_context *ctx)
 #ifdef CONFIG_X86
 struct dccg *dcn1_dccg_create(struct dc_context *ctx)
 {
-	struct dc_debug *debug = &ctx->dc->debug;
+	struct dc_debug_options *debug = &ctx->dc->debug;
 	struct dc_bios *bp = ctx->dc_bios;
 	struct dc_firmware_info fw_info = { { 0 } };
 	struct dce_dccg *clk_dce = kzalloc(sizeof(*clk_dce), GFP_KERNEL);

drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c

@@ -404,7 +404,7 @@ static const struct resource_caps res_cap = {
 		.num_pll = 6,
 };
 
-static const struct dc_debug debug_defaults = {
+static const struct dc_debug_options debug_defaults = {
 		.disable_clock_gate = true,
 };
 

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c

@@ -502,7 +502,7 @@ static const struct resource_caps res_cap = {
 		.num_pll = 4,
 };
 
-static const struct dc_debug debug_defaults_drv = {
+static const struct dc_debug_options debug_defaults_drv = {
 		.sanity_checks = true,
 		.disable_dmcu = true,
 		.force_abm_enable = false,
@@ -530,7 +530,7 @@ static const struct dc_debug debug_defaults_drv = {
 		.max_downscale_src_width = 3840,
 };
 
-static const struct dc_debug debug_defaults_diags = {
+static const struct dc_debug_options debug_defaults_diags = {
 		.disable_dmcu = true,
 		.force_abm_enable = false,
 		.timing_trace = true,