Commit d144b40a authored by Wenjing Liu's avatar Wenjing Liu Committed by Alex Deucher

drm/amd/display: move dc_link_dpia logic to link_dp_dpia

Tested-by: default avatarDaniel Wheeler <Daniel.Wheeler@amd.com>
Reviewed-by: default avatarGeorge Shen <George.Shen@amd.com>
Acked-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: default avatarWenjing Liu <wenjing.liu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent a28d0bac
......@@ -66,7 +66,7 @@ include $(AMD_DC)
DISPLAY_CORE = dc.o dc_stat.o dc_link.o dc_resource.o dc_hw_sequencer.o dc_sink.o \
dc_surface.o dc_link_dp.o dc_debug.o dc_stream.o \
dc_link_enc_cfg.o dc_link_dpia.o
dc_link_enc_cfg.o
DISPLAY_CORE += dc_vm_helper.o
......
......@@ -33,7 +33,7 @@
#include "gpio_service_interface.h"
#include "core_status.h"
#include "dc_link_dp.h"
#include "dc_link_dpia.h"
#include "link/link_dp_dpia.h"
#include "link/link_ddc.h"
#include "link_hwss.h"
#include "link.h"
......
......@@ -37,7 +37,7 @@
#include "dpcd_defs.h"
#include "dc_dmub_srv.h"
#include "dce/dmub_hw_lock_mgr.h"
#include "inc/dc_link_dpia.h"
#include "link/link_dp_dpia.h"
#include "inc/link_enc_cfg.h"
#include "link/link_dp_trace.h"
......
......@@ -24,7 +24,7 @@
# PHY, HPD, DDC and etc).
LINK = link_hwss_dio.o link_hwss_dpia.o link_hwss_hpo_dp.o link_dp_trace.o \
link_hpd.o link_ddc.o link_dpcd.o
link_hpd.o link_ddc.o link_dpcd.o link_dp_dpia.o
AMD_DAL_LINK = $(addprefix $(AMDDALPATH)/dc/link/,$(LINK))
......
......@@ -25,11 +25,12 @@
*/
#include "dc.h"
#include "dc_link_dpia.h"
#include "inc/core_status.h"
#include "dc_link.h"
#include "dc_link_dp.h"
#include "dpcd_defs.h"
#include "link_dp_dpia.h"
#include "link_hwss.h"
#include "dm_helpers.h"
#include "dmub/inc/dmub_cmd.h"
......
......@@ -27,11 +27,9 @@
#ifndef __DC_LINK_DPIA_H__
#define __DC_LINK_DPIA_H__
#include "link.h"
/* This module implements functionality for training DPIA links. */
struct dc_link;
struct dc_link_settings;
/* The approximate time (us) it takes to transmit 9 USB4 DP clock sync packets. */
#define DPIA_CLK_SYNC_DELAY 16000
......
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