PPC32: In some cases we need to make all pages _PAGE_COHERENT.

Controll this via the cpu_table flags since it's a requirement
in some CPU and host bridge combinations.
From: Adrian Cox <adrian@humboldt.co.uk>

arch/ppc/mm/hashtable.S

@@ -346,9 +346,9 @@ _GLOBAL(create_hpte)
 	rlwimi	r5,r5,32-2,31,31	/* _PAGE_USER -> PP lsb */
 	ori	r8,r8,0xe14		/* clear out reserved bits and M */
 	andc	r8,r5,r8		/* PP = user? (rw&dirty? 2: 3): 0 */
-#ifdef CONFIG_SMP
+BEGIN_FTR_SECTION
 	ori	r8,r8,_PAGE_COHERENT	/* set M (coherence required) */
-#endif
+END_FTR_SECTION_IFSET(CPU_FTR_NEED_COHERENT)
 
 	/* Construct the high word of the PPC-style PTE (r5) */
 #ifndef CONFIG_PPC64BRIDGE

arch/ppc/mm/ppc_mmu.c

@@ -137,10 +137,10 @@ void __init setbat(int index, unsigned long virt, unsigned long phys,
 	int wimgxpp;
 	union ubat *bat = BATS[index];
 
-#ifdef CONFIG_SMP
-	if ((flags & _PAGE_NO_CACHE) == 0)
+	if (((flags & _PAGE_NO_CACHE) == 0) &&
+	    (cur_cpu_spec[0]->cpu_features & CPU_FTR_NEED_COHERENT))
 		flags |= _PAGE_COHERENT;
-#endif
+
 	bl = (size >> 17) - 1;
 	if (PVR_VER(mfspr(PVR)) != 1) {
 		/* 603, 604, etc. */

include/asm-ppc/cputable.h

@@ -75,6 +75,7 @@ extern struct cpu_spec		*cur_cpu_spec[];
 #define CPU_FTR_DUAL_PLL_750FX		0x00004000
 #define CPU_FTR_NO_DPM			0x00008000
 #define CPU_FTR_HAS_HIGH_BATS		0x00010000
+#define CPU_FTR_NEED_COHERENT           0x00020000
 
 #ifdef __ASSEMBLY__