Commit d203a7ec authored by Ralf Baechle's avatar Ralf Baechle Committed by Linus Torvalds

[PATCH] Indycam / VINO drivers

Rewrite of the Indycam / VINO video v4l2 drivers for the SGI Indy.
Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
Signed-off-by: default avatarMikael Nousiainen <tmnousia@cc.hut.fi>
Cc: <video4linux-list@redhat.com>
Signed-off-by: default avatarAndrew Morton <akpm@osdl.org>
Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
parent 0bb6fcc1
...@@ -29,7 +29,7 @@ obj-$(CONFIG_VIDEO_ZORAN_LML33R10) += saa7114.o adv7170.o zr36060.o ...@@ -29,7 +29,7 @@ obj-$(CONFIG_VIDEO_ZORAN_LML33R10) += saa7114.o adv7170.o zr36060.o
obj-$(CONFIG_VIDEO_ZORAN) += zr36067.o videocodec.o obj-$(CONFIG_VIDEO_ZORAN) += zr36067.o videocodec.o
obj-$(CONFIG_VIDEO_PMS) += pms.o obj-$(CONFIG_VIDEO_PMS) += pms.o
obj-$(CONFIG_VIDEO_PLANB) += planb.o obj-$(CONFIG_VIDEO_PLANB) += planb.o
obj-$(CONFIG_VIDEO_VINO) += vino.o obj-$(CONFIG_VIDEO_VINO) += vino.o saa7191.o indycam.o
obj-$(CONFIG_VIDEO_STRADIS) += stradis.o obj-$(CONFIG_VIDEO_STRADIS) += stradis.o
obj-$(CONFIG_VIDEO_CPIA) += cpia.o obj-$(CONFIG_VIDEO_CPIA) += cpia.o
obj-$(CONFIG_VIDEO_CPIA_PP) += cpia_pp.o obj-$(CONFIG_VIDEO_CPIA_PP) += cpia_pp.o
......
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/*
* indycam.h - Silicon Graphics IndyCam digital camera driver
*
* Copyright (C) 2003 Ladislav Michl <ladis@linux-mips.org>
* Copyright (C) 2004,2005 Mikael Nousiainen <tmnousia@cc.hut.fi>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef _INDYCAM_H_
#define _INDYCAM_H_
/* I2C address for the Guinness Camera */
#define INDYCAM_ADDR 0x56
/* Camera version */
#define CAMERA_VERSION_INDY 0x10 /* v1.0 */
#define CAMERA_VERSION_MOOSE 0x12 /* v1.2 */
#define INDYCAM_VERSION_MAJOR(x) (((x) & 0xf0) >> 4)
#define INDYCAM_VERSION_MINOR(x) ((x) & 0x0f)
/* Register bus addresses */
#define INDYCAM_CONTROL 0x00
#define INDYCAM_SHUTTER 0x01
#define INDYCAM_GAIN 0x02
#define INDYCAM_BRIGHTNESS 0x03 /* read-only */
#define INDYCAM_RED_BALANCE 0x04
#define INDYCAM_BLUE_BALANCE 0x05
#define INDYCAM_RED_SATURATION 0x06
#define INDYCAM_BLUE_SATURATION 0x07
#define INDYCAM_GAMMA 0x08
#define INDYCAM_VERSION 0x0e /* read-only */
#define INDYCAM_RESET 0x0f /* write-only */
#define INDYCAM_LED 0x46
#define INDYCAM_ORIENTATION 0x47
#define INDYCAM_BUTTON 0x48
/* Field definitions of registers */
#define INDYCAM_CONTROL_AGCENA (1<<0) /* automatic gain control */
#define INDYCAM_CONTROL_AWBCTL (1<<1) /* automatic white balance */
/* 2-3 are reserved */
#define INDYCAM_CONTROL_EVNFLD (1<<4) /* read-only */
#define INDYCAM_SHUTTER_10000 0x02 /* 1/10000 second */
#define INDYCAM_SHUTTER_4000 0x04 /* 1/4000 second */
#define INDYCAM_SHUTTER_2000 0x08 /* 1/2000 second */
#define INDYCAM_SHUTTER_1000 0x10 /* 1/1000 second */
#define INDYCAM_SHUTTER_500 0x20 /* 1/500 second */
#define INDYCAM_SHUTTER_250 0x3f /* 1/250 second */
#define INDYCAM_SHUTTER_125 0x7e /* 1/125 second */
#define INDYCAM_SHUTTER_100 0x9e /* 1/100 second */
#define INDYCAM_SHUTTER_60 0x00 /* 1/60 second */
#define INDYCAM_LED_ACTIVE 0x10
#define INDYCAM_LED_INACTIVE 0x30
#define INDYCAM_ORIENTATION_BOTTOM_TO_TOP 0x40
#define INDYCAM_BUTTON_RELEASED 0x10
#define INDYCAM_SHUTTER_MIN 0x00
#define INDYCAM_SHUTTER_MAX 0xff
#define INDYCAM_GAIN_MIN 0x00
#define INDYCAM_GAIN_MAX 0xff
#define INDYCAM_RED_BALANCE_MIN 0x00 /* the effect is the opposite? */
#define INDYCAM_RED_BALANCE_MAX 0xff
#define INDYCAM_BLUE_BALANCE_MIN 0x00 /* the effect is the opposite? */
#define INDYCAM_BLUE_BALANCE_MAX 0xff
#define INDYCAM_RED_SATURATION_MIN 0x00
#define INDYCAM_RED_SATURATION_MAX 0xff
#define INDYCAM_BLUE_SATURATION_MIN 0x00
#define INDYCAM_BLUE_SATURATION_MAX 0xff
#define INDYCAM_GAMMA_MIN 0x00
#define INDYCAM_GAMMA_MAX 0xff
/* Driver interface definitions */
#define INDYCAM_VALUE_ENABLED 1
#define INDYCAM_VALUE_DISABLED 0
#define INDYCAM_VALUE_UNCHANGED -1
/* When setting controls, a value of -1 leaves the control unchanged. */
struct indycam_control {
int agc; /* boolean */
int awb; /* boolean */
int shutter;
int gain;
int red_balance;
int blue_balance;
int red_saturation;
int blue_saturation;
int gamma;
};
#define DECODER_INDYCAM_GET_CONTROLS _IOR('d', 193, struct indycam_control)
#define DECODER_INDYCAM_SET_CONTROLS _IOW('d', 194, struct indycam_control)
/* Default values for controls */
#define INDYCAM_AGC_DEFAULT INDYCAM_VALUE_ENABLED
#define INDYCAM_AWB_DEFAULT INDYCAM_VALUE_ENABLED
#define INDYCAM_SHUTTER_DEFAULT INDYCAM_SHUTTER_60
#define INDYCAM_GAIN_DEFAULT 0x80
#define INDYCAM_RED_BALANCE_DEFAULT 0x18
#define INDYCAM_BLUE_BALANCE_DEFAULT 0xa4
#define INDYCAM_RED_SATURATION_DEFAULT 0x80
#define INDYCAM_BLUE_SATURATION_DEFAULT 0xc0
#define INDYCAM_GAMMA_DEFAULT 0x80
#endif
This diff is collapsed.
/*
* saa7191.h - Philips SAA7191 video decoder driver
*
* Copyright (C) 2003 Ladislav Michl <ladis@linux-mips.org>
* Copyright (C) 2004,2005 Mikael Nousiainen <tmnousia@cc.hut.fi>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef _SAA7191_H_
#define _SAA7191_H_
/* Philips SAA7191 DMSD I2C bus address */
#define SAA7191_ADDR 0x8a
/* Register subaddresses. */
#define SAA7191_REG_IDEL 0x00
#define SAA7191_REG_HSYB 0x01
#define SAA7191_REG_HSYS 0x02
#define SAA7191_REG_HCLB 0x03
#define SAA7191_REG_HCLS 0x04
#define SAA7191_REG_HPHI 0x05
#define SAA7191_REG_LUMA 0x06
#define SAA7191_REG_HUEC 0x07
#define SAA7191_REG_CKTQ 0x08
#define SAA7191_REG_CKTS 0x09
#define SAA7191_REG_PLSE 0x0a
#define SAA7191_REG_SESE 0x0b
#define SAA7191_REG_GAIN 0x0c
#define SAA7191_REG_STDC 0x0d
#define SAA7191_REG_IOCK 0x0e
#define SAA7191_REG_CTL3 0x0f
#define SAA7191_REG_CTL4 0x10
#define SAA7191_REG_CHCV 0x11
#define SAA7191_REG_HS6B 0x14
#define SAA7191_REG_HS6S 0x15
#define SAA7191_REG_HC6B 0x16
#define SAA7191_REG_HC6S 0x17
#define SAA7191_REG_HP6I 0x18
#define SAA7191_REG_STATUS 0xff /* not really a subaddress */
/* Status Register definitions */
#define SAA7191_STATUS_CODE 0x01 /* color detected flag */
#define SAA7191_STATUS_FIDT 0x20 /* format type NTSC/PAL */
#define SAA7191_STATUS_HLCK 0x40 /* PLL unlocked/locked */
#define SAA7191_STATUS_STTC 0x80 /* tv/vtr time constant */
/* Luminance Control Register definitions */
#define SAA7191_LUMA_BYPS 0x80
/* Chroma Gain Control Settings Register definitions */
/* 0=automatic colour-killer enabled, 1=forced colour on */
#define SAA7191_GAIN_COLO 0x80
/* Standard/Mode Control Register definitions */
/* tv/vtr mode bit: 0=TV mode (slow time constant),
* 1=VTR mode (fast time constant) */
#define SAA7191_STDC_VTRC 0x80
/* SECAM mode bit: 0=other standards, 1=SECAM */
#define SAA7191_STDC_SECS 0x01
/* the bit fields above must be or'd with this value */
#define SAA7191_STDC_VALUE 0x0c
/* I/O and Clock Control Register definitions */
/* horizontal clock PLL: 0=PLL closed,
* 1=PLL circuit open and horizontal freq fixed */
#define SAA7191_IOCK_HPLL 0x80
/* S-VHS bit (chrominance from CVBS or from chrominance input):
* 0=controlled by BYPS-bit, 1=from chrominance input */
#define SAA7191_IOCK_CHRS 0x04
/* general purpose switch 2
* VINO-specific: 0=used with CVBS, 1=used with S-Video */
#define SAA7191_IOCK_GPSW2 0x02
/* general purpose switch 1 */
/* VINO-specific: 0=always, 1=not used!*/
#define SAA7191_IOCK_GPSW1 0x01
/* Miscellaneous Control #1 Register definitions */
/* automatic field detection (50/60Hz standard) */
#define SAA7191_CTL3_AUFD 0x80
/* field select: (if AUFD=0)
* 0=50Hz (625 lines), 1=60Hz (525 lines) */
#define SAA7191_CTL3_FSEL 0x40
/* the bit fields above must be or'd with this value */
#define SAA7191_CTL3_VALUE 0x19
/* Chrominance Gain Control Register definitions
* (nominal value for UV CCIR level) */
#define SAA7191_CHCV_NTSC 0x2c
#define SAA7191_CHCV_PAL 0x59
/* Driver interface definitions */
#define SAA7191_INPUT_COMPOSITE 0
#define SAA7191_INPUT_SVIDEO 1
#define SAA7191_NORM_AUTO 0
#define SAA7191_NORM_PAL 1
#define SAA7191_NORM_NTSC 2
#define SAA7191_NORM_SECAM 3
#define SAA7191_VALUE_ENABLED 1
#define SAA7191_VALUE_DISABLED 0
#define SAA7191_VALUE_UNCHANGED -1
struct saa7191_status {
/* 0=no signal, 1=signal active*/
int signal;
/* 0=50hz (pal) signal, 1=60hz (ntsc) signal */
int ntsc;
/* 0=no color detected, 1=color detected */
int color;
/* current SAA7191_INPUT_ */
int input;
/* current SAA7191_NORM_ */
int norm;
};
#define SAA7191_HUE_MIN 0x00
#define SAA7191_HUE_MAX 0xff
#define SAA7191_HUE_DEFAULT 0x80
#define SAA7191_VTRC_MIN 0x00
#define SAA7191_VTRC_MAX 0x01
#define SAA7191_VTRC_DEFAULT 0x00
struct saa7191_control {
int hue;
int vtrc;
};
#define DECODER_SAA7191_GET_STATUS _IOR('d', 195, struct saa7191_status)
#define DECODER_SAA7191_SET_NORM _IOW('d', 196, int)
#define DECODER_SAA7191_GET_CONTROLS _IOR('d', 197, struct saa7191_control)
#define DECODER_SAA7191_SET_CONTROLS _IOW('d', 198, struct saa7191_control)
#endif
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/* /*
* Driver for the VINO (Video In No Out) system found in SGI Indys.
*
* This file is subject to the terms and conditions of the GNU General Public
* License version 2 as published by the Free Software Foundation.
*
* Copyright (C) 1999 Ulf Karlsson <ulfc@bun.falkenberg.se> * Copyright (C) 1999 Ulf Karlsson <ulfc@bun.falkenberg.se>
* Copyright (C) 2003 Ladislav Michl <ladis@linux-mips.org> * Copyright (C) 2003 Ladislav Michl <ladis@linux-mips.org>
*/ */
#ifndef VINO_H #ifndef _VINO_H_
#define VINO_H #define _VINO_H_
#define VINO_BASE 0x00080000 /* Vino is in the EISA address space, #define VINO_BASE 0x00080000 /* Vino is in the EISA address space,
* but it is not an EISA bus card */ * but it is not an EISA bus card */
#define VINO_PAGE_SIZE 4096
struct sgi_vino_channel { struct sgi_vino_channel {
u32 _pad_alpha; u32 _pad_alpha;
...@@ -21,8 +27,9 @@ struct sgi_vino_channel { ...@@ -21,8 +27,9 @@ struct sgi_vino_channel {
u32 _pad_clip_end; u32 _pad_clip_end;
volatile u32 clip_end; volatile u32 clip_end;
#define VINO_FRAMERT_FULL 0xfff
#define VINO_FRAMERT_PAL (1<<0) /* 0=NTSC 1=PAL */ #define VINO_FRAMERT_PAL (1<<0) /* 0=NTSC 1=PAL */
#define VINO_FRAMERT_RT(x) (((x) & 0x1fff) << 1) /* bits 1:12 */ #define VINO_FRAMERT_RT(x) (((x) & 0xfff) << 1) /* bits 1:12 */
u32 _pad_frame_rate; u32 _pad_frame_rate;
volatile u32 frame_rate; volatile u32 frame_rate;
...@@ -67,18 +74,18 @@ struct sgi_vino { ...@@ -67,18 +74,18 @@ struct sgi_vino {
volatile u32 rev_id; volatile u32 rev_id;
#define VINO_CTRL_LITTLE_ENDIAN (1<<0) #define VINO_CTRL_LITTLE_ENDIAN (1<<0)
#define VINO_CTRL_A_FIELD_TRANS_INT (1<<1) /* Field transferred int */ #define VINO_CTRL_A_EOF_INT (1<<1) /* Field transferred int */
#define VINO_CTRL_A_FIFO_OF_INT (1<<2) /* FIFO overflow int */ #define VINO_CTRL_A_FIFO_INT (1<<2) /* FIFO overflow int */
#define VINO_CTRL_A_END_DESC_TBL_INT (1<<3) /* End of desc table int */ #define VINO_CTRL_A_EOD_INT (1<<3) /* End of desc table int */
#define VINO_CTRL_A_INT (VINO_CTRL_A_FIELD_TRANS_INT | \ #define VINO_CTRL_A_INT (VINO_CTRL_A_EOF_INT | \
VINO_CTRL_A_FIFO_OF_INT | \ VINO_CTRL_A_FIFO_INT | \
VINO_CTRL_A_END_DESC_TBL_INT) VINO_CTRL_A_EOD_INT)
#define VINO_CTRL_B_FIELD_TRANS_INT (1<<4) /* Field transferred int */ #define VINO_CTRL_B_EOF_INT (1<<4) /* Field transferred int */
#define VINO_CTRL_B_FIFO_OF_INT (1<<5) /* FIFO overflow int */ #define VINO_CTRL_B_FIFO_INT (1<<5) /* FIFO overflow int */
#define VINO_CTRL_B_END_DESC_TBL_INT (1<<6) /* End of desc table int */ #define VINO_CTRL_B_EOD_INT (1<<6) /* End of desc table int */
#define VINO_CTRL_B_INT (VINO_CTRL_B_FIELD_TRANS_INT | \ #define VINO_CTRL_B_INT (VINO_CTRL_B_EOF_INT | \
VINO_CTRL_B_FIFO_OF_INT | \ VINO_CTRL_B_FIFO_INT | \
VINO_CTRL_B_END_DESC_TBL_INT) VINO_CTRL_B_EOD_INT)
#define VINO_CTRL_A_DMA_ENBL (1<<7) #define VINO_CTRL_A_DMA_ENBL (1<<7)
#define VINO_CTRL_A_INTERLEAVE_ENBL (1<<8) #define VINO_CTRL_A_INTERLEAVE_ENBL (1<<8)
#define VINO_CTRL_A_SYNC_ENBL (1<<9) #define VINO_CTRL_A_SYNC_ENBL (1<<9)
...@@ -104,18 +111,18 @@ struct sgi_vino { ...@@ -104,18 +111,18 @@ struct sgi_vino {
u32 _pad_control; u32 _pad_control;
volatile u32 control; volatile u32 control;
#define VINO_INTSTAT_A_FIELD_TRANS (1<<0) /* Field transferred int */ #define VINO_INTSTAT_A_EOF (1<<0) /* Field transferred int */
#define VINO_INTSTAT_A_FIFO_OF (1<<1) /* FIFO overflow int */ #define VINO_INTSTAT_A_FIFO (1<<1) /* FIFO overflow int */
#define VINO_INTSTAT_A_END_DESC_TBL (1<<2) /* End of desc table int */ #define VINO_INTSTAT_A_EOD (1<<2) /* End of desc table int */
#define VINO_INTSTAT_A (VINO_INTSTAT_A_FIELD_TRANS | \ #define VINO_INTSTAT_A (VINO_INTSTAT_A_EOF | \
VINO_INTSTAT_A_FIFO_OF | \ VINO_INTSTAT_A_FIFO | \
VINO_INTSTAT_A_END_DESC_TBL) VINO_INTSTAT_A_EOD)
#define VINO_INTSTAT_B_FIELD_TRANS (1<<3) /* Field transferred int */ #define VINO_INTSTAT_B_EOF (1<<3) /* Field transferred int */
#define VINO_INTSTAT_B_FIFO_OF (1<<4) /* FIFO overflow int */ #define VINO_INTSTAT_B_FIFO (1<<4) /* FIFO overflow int */
#define VINO_INTSTAT_B_END_DESC_TBL (1<<5) /* End of desc table int */ #define VINO_INTSTAT_B_EOD (1<<5) /* End of desc table int */
#define VINO_INTSTAT_B (VINO_INTSTAT_B_FIELD_TRANS | \ #define VINO_INTSTAT_B (VINO_INTSTAT_B_EOF | \
VINO_INTSTAT_B_FIFO_OF | \ VINO_INTSTAT_B_FIFO | \
VINO_INTSTAT_B_END_DESC_TBL) VINO_INTSTAT_B_EOD)
u32 _pad_intr_status; u32 _pad_intr_status;
volatile u32 intr_status; volatile u32 intr_status;
......
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