Commit d214d0c2 authored by Ian Rogers's avatar Ian Rogers Committed by Arnaldo Carvalho de Melo

perf vendor events: Update Intel icelakex

Update to v1.15, the metrics are based on TMA 4.4 full.

Use script at:
https://github.com/intel/event-converter-for-linux-perf/blob/master/download_and_gen.py

to download and generate the latest events and metrics. Manually copy
the icelakex files into perf and update mapfile.csv.

Tested with 'perf test':
 10: PMU events                                                      :
 10.1: PMU event table sanity                                        : Ok
 10.2: PMU event map aliases                                         : Ok
 10.3: Parsing of PMU event table metrics                            : Ok
 10.4: Parsing of PMU event table metrics with fake PMUs             : Ok
 90: perf all metricgroups test                                      : Ok
 91: perf all metrics test                                           : Skip
 93: perf all PMU test                                               : Ok
Signed-off-by: default avatarIan Rogers <irogers@google.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: James Clark <james.clark@arm.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.garry@huawei.com>
Cc: Kan Liang <kan.liang@linux.intel.com>
Cc: Kshipra Bopardikar <kshipra.bopardikar@intel.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Perry Taylor <perry.taylor@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Sedat Dilek <sedat.dilek@gmail.com>
Cc: Stephane Eranian <eranian@google.com>
Cc: Xing Zhengjun <zhengjun.xing@linux.intel.com>
Link: http://lore.kernel.org/lkml/20220727220832.2865794-14-irogers@google.comSigned-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent a4a4353e
...@@ -291,7 +291,7 @@ ...@@ -291,7 +291,7 @@
"UMask": "0x4f" "UMask": "0x4f"
}, },
{ {
"BriefDescription": "All retired load instructions.", "BriefDescription": "Retired load instructions.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"Data_LA": "1", "Data_LA": "1",
...@@ -299,12 +299,12 @@ ...@@ -299,12 +299,12 @@
"EventName": "MEM_INST_RETIRED.ALL_LOADS", "EventName": "MEM_INST_RETIRED.ALL_LOADS",
"PEBS": "1", "PEBS": "1",
"PEBScounters": "0,1,2,3", "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts all retired load instructions. This event accounts for SW prefetch instructions for loads.", "PublicDescription": "Counts all retired load instructions. This event accounts for SW prefetch instructions of PREFETCHNTA or PREFETCHT0/1/2 or PREFETCHW.",
"SampleAfterValue": "1000003", "SampleAfterValue": "1000003",
"UMask": "0x81" "UMask": "0x81"
}, },
{ {
"BriefDescription": "All retired store instructions.", "BriefDescription": "Retired store instructions.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"Data_LA": "1", "Data_LA": "1",
...@@ -313,7 +313,7 @@ ...@@ -313,7 +313,7 @@
"L1_Hit_Indication": "1", "L1_Hit_Indication": "1",
"PEBS": "1", "PEBS": "1",
"PEBScounters": "0,1,2,3", "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts all retired store instructions. This event account for SW prefetch instructions and PREFETCHW instruction for stores.", "PublicDescription": "Counts all retired store instructions.",
"SampleAfterValue": "1000003", "SampleAfterValue": "1000003",
"UMask": "0x82" "UMask": "0x82"
}, },
...@@ -409,7 +409,6 @@ ...@@ -409,7 +409,6 @@
"PEBScounters": "0,1,2,3", "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts retired load instructions whose data sources were HitM responses from shared L3.", "PublicDescription": "Counts retired load instructions whose data sources were HitM responses from shared L3.",
"SampleAfterValue": "20011", "SampleAfterValue": "20011",
"Speculative": "1",
"UMask": "0x4" "UMask": "0x4"
}, },
{ {
...@@ -473,7 +472,6 @@ ...@@ -473,7 +472,6 @@
"PEBScounters": "0,1,2,3", "PEBScounters": "0,1,2,3",
"PublicDescription": "Counts retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache.", "PublicDescription": "Counts retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache.",
"SampleAfterValue": "20011", "SampleAfterValue": "20011",
"Speculative": "1",
"UMask": "0x2" "UMask": "0x2"
}, },
{ {
...@@ -867,7 +865,7 @@ ...@@ -867,7 +865,7 @@
"UMask": "0x1" "UMask": "0x1"
}, },
{ {
"BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that hit in the L3 or were snooped from another core's caches on the same socket.", "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that hit in the L3 or were snooped from another core's caches on the same socket.",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OCR.READS_TO_CORE.L3_HIT", "EventName": "OCR.READS_TO_CORE.L3_HIT",
...@@ -878,7 +876,7 @@ ...@@ -878,7 +876,7 @@
"UMask": "0x1" "UMask": "0x1"
}, },
{ {
"BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop hit a modified line in another core's caches which forwarded the data.", "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop hit a modified line in another core's caches which forwarded the data.",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HITM", "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HITM",
...@@ -889,7 +887,7 @@ ...@@ -889,7 +887,7 @@
"UMask": "0x1" "UMask": "0x1"
}, },
{ {
"BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop that hit in another core, which did not forward the data.", "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop that hit in another core, which did not forward the data.",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HIT_NO_FWD", "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HIT_NO_FWD",
...@@ -900,7 +898,7 @@ ...@@ -900,7 +898,7 @@
"UMask": "0x1" "UMask": "0x1"
}, },
{ {
"BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop hit in another core's caches which forwarded the unmodified data to the requesting core.", "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop hit in another core's caches which forwarded the unmodified data to the requesting core.",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HIT_WITH_FWD", "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HIT_WITH_FWD",
...@@ -911,7 +909,7 @@ ...@@ -911,7 +909,7 @@
"UMask": "0x1" "UMask": "0x1"
}, },
{ {
"BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop was sent and data was returned (Modified or Not Modified).", "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop was sent and data was returned (Modified or Not Modified).",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_FWD", "EventName": "OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_FWD",
...@@ -922,7 +920,7 @@ ...@@ -922,7 +920,7 @@
"UMask": "0x1" "UMask": "0x1"
}, },
{ {
"BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop hit a modified line in another core's caches which forwarded the data.", "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop hit a modified line in another core's caches which forwarded the data.",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HITM", "EventName": "OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HITM",
...@@ -933,7 +931,7 @@ ...@@ -933,7 +931,7 @@
"UMask": "0x1" "UMask": "0x1"
}, },
{ {
"BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop hit in another core's caches which forwarded the unmodified data to the requesting core.", "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop hit in another core's caches which forwarded the unmodified data to the requesting core.",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HIT_WITH_FWD", "EventName": "OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HIT_WITH_FWD",
...@@ -944,7 +942,7 @@ ...@@ -944,7 +942,7 @@
"UMask": "0x1" "UMask": "0x1"
}, },
{ {
"BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.", "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OCR.READS_TO_CORE.SNC_CACHE.HITM", "EventName": "OCR.READS_TO_CORE.SNC_CACHE.HITM",
...@@ -955,7 +953,7 @@ ...@@ -955,7 +953,7 @@
"UMask": "0x1" "UMask": "0x1"
}, },
{ {
"BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.", "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OCR.READS_TO_CORE.SNC_CACHE.HIT_WITH_FWD", "EventName": "OCR.READS_TO_CORE.SNC_CACHE.HIT_WITH_FWD",
......
...@@ -99,4 +99,4 @@ ...@@ -99,4 +99,4 @@
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"UMask": "0x2" "UMask": "0x2"
} }
] ]
\ No newline at end of file
...@@ -481,4 +481,4 @@ ...@@ -481,4 +481,4 @@
"Speculative": "1", "Speculative": "1",
"UMask": "0x1" "UMask": "0x1"
} }
] ]
\ No newline at end of file
...@@ -306,7 +306,7 @@ ...@@ -306,7 +306,7 @@
"UMask": "0x1" "UMask": "0x1"
}, },
{ {
"BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches.", "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches.",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OCR.READS_TO_CORE.L3_MISS", "EventName": "OCR.READS_TO_CORE.L3_MISS",
...@@ -317,7 +317,7 @@ ...@@ -317,7 +317,7 @@
"UMask": "0x1" "UMask": "0x1"
}, },
{ {
"BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches and were supplied by the local socket.", "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches and were supplied by the local socket.",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OCR.READS_TO_CORE.L3_MISS_LOCAL", "EventName": "OCR.READS_TO_CORE.L3_MISS_LOCAL",
...@@ -328,7 +328,7 @@ ...@@ -328,7 +328,7 @@
"UMask": "0x1" "UMask": "0x1"
}, },
{ {
"BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that missed the L3 Cache and were supplied by the local socket (DRAM or PMM), whether or not in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts PMM or DRAM accesses that are controlled by the close or distant SNC Cluster.", "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that missed the L3 Cache and were supplied by the local socket (DRAM or PMM), whether or not in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts PMM or DRAM accesses that are controlled by the close or distant SNC Cluster.",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB", "EventCode": "0xB7, 0xBB",
"EventName": "OCR.READS_TO_CORE.L3_MISS_LOCAL_SOCKET", "EventName": "OCR.READS_TO_CORE.L3_MISS_LOCAL_SOCKET",
......
...@@ -214,6 +214,18 @@ ...@@ -214,6 +214,18 @@
"SampleAfterValue": "50021", "SampleAfterValue": "50021",
"UMask": "0x20" "UMask": "0x20"
}, },
{
"BriefDescription": "This event counts the number of mispredicted ret instructions retired. Non PEBS",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.RET",
"PEBS": "1",
"PEBScounters": "0,1,2,3,4,5,6,7",
"PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts mispredicted return instructions retired.",
"SampleAfterValue": "50021",
"UMask": "0x8"
},
{ {
"BriefDescription": "Cycle counts are evenly distributed between active threads in the Core.", "BriefDescription": "Cycle counts are evenly distributed between active threads in the Core.",
"CollectPEBSRecord": "2", "CollectPEBSRecord": "2",
......
...@@ -266,4 +266,4 @@ ...@@ -266,4 +266,4 @@
"Speculative": "1", "Speculative": "1",
"UMask": "0x20" "UMask": "0x20"
} }
] ]
\ No newline at end of file
...@@ -11,6 +11,7 @@ GenuineIntel-6-7A,v1.01,goldmontplus,core ...@@ -11,6 +11,7 @@ GenuineIntel-6-7A,v1.01,goldmontplus,core
GenuineIntel-6-(3C|45|46),v31,haswell,core GenuineIntel-6-(3C|45|46),v31,haswell,core
GenuineIntel-6-3F,v25,haswellx,core GenuineIntel-6-3F,v25,haswellx,core
GenuineIntel-6-(7D|7E|A7),v1.14,icelake,core GenuineIntel-6-(7D|7E|A7),v1.14,icelake,core
GenuineIntel-6-6[AC],v1.15,icelakex,core
GenuineIntel-6-3A,v18,ivybridge,core GenuineIntel-6-3A,v18,ivybridge,core
GenuineIntel-6-3E,v19,ivytown,core GenuineIntel-6-3E,v19,ivytown,core
GenuineIntel-6-2D,v20,jaketown,core GenuineIntel-6-2D,v20,jaketown,core
...@@ -31,8 +32,6 @@ GenuineIntel-6-25,v2,westmereep-sp,core ...@@ -31,8 +32,6 @@ GenuineIntel-6-25,v2,westmereep-sp,core
GenuineIntel-6-2F,v2,westmereex,core GenuineIntel-6-2F,v2,westmereex,core
GenuineIntel-6-55-[01234],v1,skylakex,core GenuineIntel-6-55-[01234],v1,skylakex,core
GenuineIntel-6-8[CD],v1,tigerlake,core GenuineIntel-6-8[CD],v1,tigerlake,core
GenuineIntel-6-6A,v1,icelakex,core
GenuineIntel-6-6C,v1,icelakex,core
GenuineIntel-6-86,v1,snowridgex,core GenuineIntel-6-86,v1,snowridgex,core
GenuineIntel-6-8F,v1,sapphirerapids,core GenuineIntel-6-8F,v1,sapphirerapids,core
AuthenticAMD-23-([12][0-9A-F]|[0-9A-F]),v2,amdzen1,core AuthenticAMD-23-([12][0-9A-F]|[0-9A-F]),v2,amdzen1,core
......
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